參數(shù)資料
型號: PCD5002A
廠商: NXP Semiconductors N.V.
英文描述: Enhanced Pager Decoder for APOC1/POCSAG
中文描述: 增強傳呼機解碼器APOC1/POCSAG
文件頁數(shù): 38/48頁
文件大小: 252K
代理商: PCD5002A
1999 Jan 08
38
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
14 AC CHARACTERISTICS
V
DD
= 2.7 V; V
SS
= 0 V; V
PR
= 2.7 V; T
amb
= 25
°
C;. f
osc
= 76800 Hz.
SYMBOLS
PARAMETER
CONDITIONS
MIN.
TYP.
MAX.
UNIT
System clock
T
clk
system clock period
f
osc
= 76800 Hz
13.02
μ
s
Call alert frequencies
f
AL
alert frequency
SPF byte 03H; bits
D1 and D0 = 0 0
D1 and D0 = 0 1
D1 and D0 = 1 0
D1 and D0 = 1 1
alert set-up bit D2 = 1; outputs
ATL, ATH and LED
alert set-up bit D2 = 1; outputs
ATL and ATH
alert set-up bit D2 = 1; outputs
ATL and ATH
low-level alert
2048
2731
3200
4096
16
Hz
Hz
Hz
Hz
Hz
f
AW
warbled alert; modulation
frequency
warbled alert; high acoustic
alert frequency
warbled alert; low acoustic alert
frequency
pulsed vibrator frequency
(square wave)
f
AWH
f
AL
Hz
f
AWL
1
2
f
AL
Hz
f
VBP
25
Hz
Call alert duration
t
ALT
t
ALL
t
ALH
t
VBL
t
VBH
t
ALC
t
ALP
alert time-out period
ATL output time-out period
ATH output time-out period
VIB output time-out period
VIB output time-out period
alert cycle period
alert pulse duration
16
4
12
4
12
1
125
s
s
s
s
s
s
ms
low-level alert
high-level alert
low-level alert
high-level alert
Real-time clock reference
f
ref
real-time clock reference
frequency
SPF byte 02H; bits
D3 and D2 = 0 0; note 1
D3 and D2 = 0 1; note 2
D3 and D2 = 1 0
D3 and D2 = 1 1
all reference frequencies except
50 Hz (square wave)
32768
50
2
1
60
13.02
Hz
Hz
Hz
Hz
μ
s
t
RFP
real-time clock reference pulse
duration
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