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參數(shù)資料
| 型號： | PCD5002A |
| 廠商： | NXP Semiconductors N.V. |
| 英文描述： | Enhanced Pager Decoder for APOC1/POCSAG |
| 中文描述： | 增強傳呼機解碼器APOC1/POCSAG |
| 文件頁數(shù)： | 26/48頁 |
| 文件大小： | 252K |
| 代理商： | PCD5002A |
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1999 Jan 08
26
Philips Semiconductors
Product specification
Enhanced Pager Decoder for
APOC1/POCSAG
PCD5002A
Fig.11 POCSAG alert timing.
handbook, full pagewidth
FC = 00
FC = 01
FC = 10
FC = 11
tALC
tALP
tALC
tALC
tALC
tALC
tALP
tALP
tALP
tALP
tALP
tALP
MLC252
8.44
Cancelling alerts
Standard POCSAG alerts (manual or automatic) are
cancelled by resetting bit D0 in the alert set-up register.
User defined alerts are cancelled by writing a zero to the
alert cadence register. Any ongoing alert is cancelled
when a reset pulse is applied to input RST.
8.45
Automatic POCSAG alerts
Standard alert patterns have been defined for each
POCSAG call type, as indicated by the function bits in the
address code-word (see Table 1). The timing of these alert
patterns is shown in Fig.11. After completion of the full 16 s
alert period an interrupt is generated by status bit D4.
When enabled by SPF programming (SPF byte 03, bit D2)
standard POCSAG alerts will be automatically generated
at outputs ATL, ATH, LED and VIB upon call reception.
The alert pattern matches the call type as indicated by the
function bits in the received address code-word.
The original settings of the alert set-up register will be lost.
Bit D0 is reset after completion of the alert.
8.46
SRAM access
The on-chip SRAM can hold up to 96 bytes of call data.
Each call consists of a call header (3 bytes), message data
blocks (3 bytes per code-word) and a call terminator
(3 bytes).
The RAM is filled by the decoder and can be read via the
I
2
C-bus interface. The RAM is accessed indirectly by a
read address pointer and a data output register. A write
address pointer indicates the position of the last message
byte stored.
Status register bit D2 is set when the read and write
pointers are different. It is reset only when the SRAM
pointers become equal during reading, i.e. when the RAM
becomes empty.
Status bit D3 is set when the read and write pointers
become equal. This can be due to a RAM empty or a RAM
full condition. It is reset after a status read operation.
Interrupts are generated as follows:
When status bit D2 is set and the receiver is disabled
(RXE = 0); data is available for reading, if data fail mode
(short fade recovery mode in APOC1) is not active
Immediately when status bit D3 is set: RAM is either
empty (status bit D2 = 0) or full (status bit D2 = 1).
To avoid loss of data due to RAM overflow at least 3 bytes
of data must be read during reception of the code-word
following the ‘RAM full’ interrupt.
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| PCD5002AH | Enhanced Pager Decoder for APOC1/POCSAG |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| PCD5002AH | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Enhanced Pager Decoder for APOC1/POCSAG |
| PCD5002H | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
| PCD5002HBD-S | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002HBD-T | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Telecommunication Decoder |
| PCD5002U/10 | 制造商:PHILIPS 制造商全稱:NXP Semiconductors 功能描述:Advanced POCSAG and APOC-1 Paging Decoder |
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