參數(shù)資料
型號(hào): PCADADIO-CS
英文描述: PC(ISA)BUS I/O CARD
中文描述: 電腦(ISA)總線的I / O卡
文件頁(yè)數(shù): 9/26頁(yè)
文件大?。?/td> 393K
代理商: PCADADIO-CS
Page 9
2192-09061-000-000
J489 PCADADIO
ADC Triggering
The counter/timer trigger uses channel A and the hardware strobe the /RCONV pin on PL1.
Conversion is started from these sources when OUTA signal or /RCONV are low. To ensure that
the ADC does not perform multiple conversions it must be ensured that hardware and CTC
trigger pulses are greater than 250nS, but less than 6
μ
S.
Maximum data throughput can be obtained by triggering a new conversion before data from the
last conversion is read and processed. To ensure that the ADC data registers contain data from
the last conversion they must be read within 6
μ
S of triggering a new conversion.
6
μ
s max
250ns min
/RCONV
or
OUTA
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