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參數(shù)資料
| 型號： | PCADADIO-CS |
| 英文描述： | PC(ISA)BUS I/O CARD |
| 中文描述： | 電腦（ISA）總線的I / O卡 |
| 文件頁數(shù)： | 8/26頁 |
| 文件大?。?/td> | 393K |
| 代理商： | PCADADIO-CS |
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Page 8
2192-09061-000-000
J489 PCADADIO
ADC Sequence
The PCADADIO is shipped calibrated for the ±5V range, and requires re-calibration if used on
other ranges. The ADC may be triggered from three alternative sources, selected by a jumper:
Software trigger, from writing the register
Hardware trigger, from an external TTL input, approximately 1-2
μ
sec low pulse
Periodic timer, programmed from the on-board CTC
In the second two cases an interrupt should be used to signal that a new value is ready.
With a software trigger all timing can be done from the program using this sequence:
Select channel register and write channel value
Delay for input settling (about 50
μ
sec)
Select software trigger register and write to trigger (value not defined)
Delay for ADC conversion (about 20
μ
sec)
Select status register and read to check that new value is ready
Read ADC data registers
DAC Sequence
Before writing a 12-bit DAC value to the data registers at Base + 2 and Base + 3, the DAC
channel must be selected. Write value 02 to the Pointer register for DAC A and value 03 for
DAC B.
Digital I/Os
The direction of individual nibbles can be switched by writing to the digital configuration register.
Access to the individual outputs and inputs is via the digital I/O group 2 and 3 registers. If a
nibble is configured as an input a write to the output register will have no effect on the input,
unless the state of the configuration register is changed to an output. In this case the last value
written to the nibble will be transferred to the output. It is therefore important to ensure that the
correct value is written to the output register before switching from an input to an output.
Counter/Timers
The PCADADIO contains three 16-bit counter/timers in an Intel 8254-compatible Counter Timer
Chip (CTC).
To offer maximum flexibility, the PCADADIO has a 10-way connector (PL3) with the facility to link
the inputs to external and internal clock sources including the outputs of other counter/timer
channels. Additionally, channel A can be used to start ADC conversion and channel B to
generate interrupts on IRQ2 or 3 when links LK10 and LK4 are selected respectively.
Counter A should always be programmed in mode 2 which ensures that OUTA is only active for
a single clock cycle (i.e.1
μ
s when connected to the 1MHz clock). When OUTC is connected to
CLKA, the time between rising edges on OUTC must not exceed 6
μ
s or be less than 250ns.
Before connecting any inputs to the digital I/Os, check that the links (LK12-15) which
control the reset state of the individual nibbles are correctly configured as inputs,
otherwise damage may occur, either to the PCADADIO or external equipment.
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相關(guān)代理商/技術(shù)參數(shù) |
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|---|---|
| PCAF-1 | 制造商:Aeroflex / KDI 功能描述:ATTENUATOR - PCB MOUNT |
| PCAF-10 | 制造商:Aeroflex / KDI 功能描述:ATTENUATOR - PCB MOUNT |
| PCAF-2 | 制造商:Aeroflex / KDI 功能描述:ATTENUATOR - PCB MOUNT |
| PCAF-20 | 制造商:Aeroflex / KDI 功能描述:ATTENUATOR - PCB MOUNT 制造商:Aeroflex 功能描述: |
| PCAF-3 | 制造商:Aeroflex / KDI 功能描述:ATTENUATOR - PCB MOUNT |
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