參數(shù)資料
型號: PCA9673D
廠商: NXP Semiconductors N.V.
元件分類: I2C/I2S
英文描述: Remote 16-bit I-O expander for Fm+ I2C-bus with interrupt and reset
封裝: PCA9673BQ<SOT815-1 (DHVQFN24)|<<http://www.nxp.com/packages/SOT815-1.html<1<Always Pb-free,;PCA9673BS<SOT616-1 (HVQFN24)|<<http://www.nxp.com/packages/SOT616-1.html<1&
文件頁數(shù): 22/33頁
文件大?。?/td> 283K
代理商: PCA9673D
PCA9673
All information provided in this document is subject to legal disclaimers.
NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 29 September 2011
22 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
[3]
C
b
= total capacitance of one bus line in pF.
A master device must internally provide a hold time of at least 300 ns for the SDA signal (refer to the V
IL
of the SCL signal) in order to
bridge the undefined region SCL’s falling edge.
[4]
[5]
The maximum t
f
for the SDA and SCL bus lines is specified at 300 ns. The maximum fall time for the SDA output stage t
f
is specified at
250 ns. This allows series protection resistors to be connected between the SDA and the SCL pins and the SDA/SCL bus lines without
exceeding the maximum specified t
f
.
Input filters on the SDA and SCL inputs suppress noise spikes less than 50 ns.
[6]
Rise and fall times refer to V
IL
and V
IH
.
Fig 24. I
2
C-bus timing diagram
002aab175
protocol
START
condition
(S)
bit 7
MSB
(A7)
bit 6
(A6)
bit 0
(R/W)
acknowledge
(A)
STOP
condition
(P)
SCL
SDA
t
HD;STA
t
SU;DAT
t
HD;DAT
t
f
t
BUF
t
SU;STA
t
LOW
t
HIGH
t
VD;ACK
t
SU;STO
1
/ f
SCL
t
r
t
VD;DAT
0.3 × V
DD
0.7 × V
DD
0.3 × V
DD
0.7 × V
DD
Fig 25. Reset timing
SDA
SCL
002aac282
t
rst
50 %
30 %
50 %
50 %
50 %
t
rec(rst)
t
w(rst)
RESET
P0n, P1n
output off
START
t
rst
ACK or read cycle
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