參數(shù)資料
型號: PCA9673D
廠商: NXP Semiconductors N.V.
元件分類: I2C/I2S
英文描述: Remote 16-bit I-O expander for Fm+ I2C-bus with interrupt and reset
封裝: PCA9673BQ<SOT815-1 (DHVQFN24)|<<http://www.nxp.com/packages/SOT815-1.html<1<Always Pb-free,;PCA9673BS<SOT616-1 (HVQFN24)|<<http://www.nxp.com/packages/SOT616-1.html<1&
文件頁數(shù): 15/33頁
文件大?。?/td> 283K
代理商: PCA9673D
PCA9673
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NXP B.V. 2011. All rights reserved.
Product data sheet
Rev. 2 — 29 September 2011
15 of 33
NXP Semiconductors
PCA9673
Remote 16-bit I/O expander for Fm+ I
2
C-bus with interrupt and reset
8.4 Power-on reset
When power is applied to V
DD
, an internal Power-On Reset (POR) holds the PCA9673 in
a reset condition until V
DD
has reached V
POR
. At that point, the reset condition is released
and the PCA9673 registers and I
2
C-bus/SMBus state machine will initialize to their default
states. Thereafter V
DD
must be lowered below 0.2 V to reset the device.
8.5 Interrupt output (INT)
The PCA9673 provides an open-drain interrupt (INT) which can be fed to a corresponding
input of the microcontroller (see
Figure 15
,
Figure 16
, and
Figure 17
). This gives these
chips a kind of master function which can initiate an action elsewhere in the system.
An interrupt is generated by any rising or falling edge of the port inputs. After time t
(v)D
the
signal INT is valid.
The interrupt disappears when data on the port is changed to the original setting or data is
read from or written to the device which has generated the interrupt.
In the write mode, the interrupt may become deactivated (HIGH) on the rising edge of the
write to port pulse. On the falling edge of the write to port pulse the interrupt is definitely
deactivated (HIGH).
The interrupt is reset in the read mode on the rising edge of the read from port pulse.
During the resetting of the interrupt itself, any changes on the I/Os may not generate an
interrupt. After the interrupt is reset any change in I/Os will be detected and transmitted as
an INT.
8.6 RESET input
A reset can be accomplished by holding the RESET pin LOW for a minimum of t
w(rst)
. The
PCA9673 registers and I
2
C-bus state machine will be held in their default state until the
RESET input is once again HIGH.
Fig 17. Application of multiple PCA9673s with interrupt
002aac308
V
DD
MICROCOMPUTER
INT
PCA9673
INT
PCA9673
INT
device 1
device 2
PCA9673
INT
device 8
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