參數(shù)資料
型號(hào): PC56F8006VLF
廠商: Freescale Semiconductor
文件頁(yè)數(shù): 96/106頁(yè)
文件大?。?/td> 0K
描述: DSP 16BIT 48-LQFP
標(biāo)準(zhǔn)包裝: 250
系列: 56F8xxx
核心處理器: 56800
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲(chǔ)器容量: 16KB(8K x 16)
程序存儲(chǔ)器類型: 閃存
RAM 容量: 1K x 16
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 24x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
Overview
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Freescale Semiconductor
9
3.3
Architecture Block Diagram
The 56F8006/56F8002’s architecture is shown in Figure 2 and Figure 3. Figure 2 illustrates how the 56800E system buses
communicate with internal memories and the IPBus interface and the internal connections among each unit of the 56800E core.
Figure 3 shows the peripherals and control blocks connected to the IPBus bridge. Please see the system integration module
(SIM) section in the MC56F8006 Reference Manual for information about which signals are multiplexed with those of other
peripherals.
Figure 2. 56800E Core Block Diagram
Data
DSP56800E Core
Arithmetic
Logic Unit
(ALU)
XAB2
PAB
PDB
CDBW
CDBR
XDB2
Program
Memory
Data/
IPBus
Interface
Bit-
Manipulation
Unit
N3
M01
Address
XAB1
Generation
Unit
(AGU)
PC
LA
LA2
HWS0
HWS1
FIRA
OMR
SR
FISR
LC
LC2
Instruction
Decoder
Interrupt
Unit
Looping
Unit
Program Control Unit
ALU1
ALU2
MAC and ALU
A1
A2
A0
B1
B2
B0
C1
C2
C0
D1
D2
D0
Y1
Y0
X0
Enhanced
JTAG TAP
R2
R3
R4
R5
SP
R0
R1
N
Y
Multi-Bit Shifter
OnCE
Program
RAM
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