參數(shù)資料
型號: PC56F8006VLF
廠商: Freescale Semiconductor
文件頁數(shù): 59/106頁
文件大?。?/td> 0K
描述: DSP 16BIT 48-LQFP
標準包裝: 250
系列: 56F8xxx
核心處理器: 56800
芯體尺寸: 16-位
速度: 32MHz
連通性: I²C,LIN,SCI,SPI
外圍設(shè)備: LVD,POR,PWM,WDT
輸入/輸出數(shù): 40
程序存儲器容量: 16KB(8K x 16)
程序存儲器類型: 閃存
RAM 容量: 1K x 16
電壓 - 電源 (Vcc/Vdd): 1.8 V ~ 3.6 V
數(shù)據(jù)轉(zhuǎn)換器: A/D 24x12b
振蕩器型: 內(nèi)部
工作溫度: -40°C ~ 105°C
封裝/外殼: 48-LQFP
包裝: 托盤
MC56F8006/MC56F8002 Digital Signal Controller, Rev. 4
Specifications
Freescale Semiconductor
56
8.11
Reset, Stop, Wait, Mode Select, and Interrupt Timing
NOTE
All address and data buses described here are internal.
Figure 24. GPIO Interrupt Timing (Negative Edge-Sensitive)
8.12
External Oscillator (XOSC) Characteristics
Reference Figure 10, and Figure 11, and Figure 12 for crystal or resonator circuits.
Table 27. Reset, Stop, Wait, Mode Select, and Interrupt Timing1,2
1 In the formulas, T = system clock cycle and T
osc = oscillator clock cycle. For an operating frequency of 32 MHz, T = 31.25 ns.
At 4 MHz (used coming out of reset and stop modes), T = 250 ns.
2 Parameters listed are guaranteed by design.
Characteristic
Symbol
Typical Min
Typical Max
Unit
See Figure
Minimum RESET Assertion Duration
tRA
4T
ns
Minimum GPIO pin Assertion for Interrupt
tIW
2T
ns
RESET deassertion to First Address Fetch
tRDA
96TOSC + 64T
97TOSC + 65T
ns
Delay from Interrupt Assertion to Fetch of first
instruction (exiting Stop)
tIF
—6T
ns
GPIO pin
(Input)
tIW
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