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參數(shù)資料
| 型號： | PC33975AR2 |
| 廠商： | 飛思卡爾半導體(中國)有限公司 |
| 英文描述： | Multiple Switch Detection Interface with Suppressed Wake-Up and 32mA Wetting Current |
| 中文描述： | 多交換檢測接口，具有抑制喚醒和32毫安濕電流 |
| 文件頁數(shù)： | 9/32頁 |
| 文件大?。?/td> | 641K |
| 代理商： | PC33975AR2 |
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Analog Integrated Circuit Device Data
Freescale Semiconductor
9
33975
DYNAMIC ELECTRICAL CHARACTERISTICS
DYNAMIC ELECTRICAL CHARACTERISTICS
Table 5. Dynamic Electrical Characteristics
Characteristics noted under conditions of 3.0 V
≤
VDD
≤
5.5 V, 8.0 V
≤
V
PWR
≤
28 V, -40
°
C
≤
T
C
≤
125
°
C unless otherwise
noted. Where applicable, typical values reflect the parameter’s approximate average value with V
PWR
= 13 V, T
A
= 25
°
C.
Characteristic
Symbol
Min
Typ
Max
Unit
SWITCH INPUT
Pulse Wetting Current Time
t
pulse
(
on
)
15
16
22
ms
Interrupt Delay Time
Normal Mode
t
int-dly
–
5.0
16
μ
s
Sleep Mode Switch Scan Time
t
scan
100
200
300
μ
s
Calibrated Scan Timer Accuracy
Sleep Mode
t
scan timer
–
–
10
%
Calibrated Interrupt Timer Accuracy
Sleep Mode
t
int timer
–
–
10
%
DIGITAL INTERFACE TIMING
(12)
Required Low State Duration on VPWR for Reset
(13)
V
PWR
≤
0.2 V
t
RESET
–
–
10
μ
s
Falling Edge of CS to Rising Edge of SCLK
Required Setup Time
t
lead
100
–
–
ns
Falling Edge of SCLK to Rising Edge of
CS
Required Setup Time
t
lag
50
–
–
ns
SI to Falling Edge of SCLK
Required Setup Time
t
SI(
su
)
16
–
–
ns
Falling Edge of SCLK to SI
Required Hold Time
t
SI(hold)
20
–
–
ns
SI,
CS
, SCLK Signal Rise Time
(14)
t
r
(SI)
–
5.0
–
ns
SI,
CS
, SCLK Signal Fall Time
(14)
t
f
(SI)
–
5.0
–
ns
Time from Falling Edge of
CS
to SO Low Impedance
(15)
t
SO(
en
)
–
–
55
ns
Time from Rising Edge of
CS
to SO High Impedance
(16)
t
SO(
dis
)
–
–
55
ns
Time from Rising Edge of SCLK to SO Data Valid
(17)
t
valid
–
25
55
ns
Notes
12.
13.
14.
15.
16.
17.
These parameters are guaranteed by design. Production test equipment uses 4.16 MHz, 5.0 V SPI interface.
This parameter is guaranteed by design but not production tested.
Rise and Fall time of incoming SI,
CS
, and SCLK signals suggested for design consideration to prevent the occurrence of double pulsing.
Time required for valid output status data to be available on SO terminal.
Time required for output states data to be terminated at SO terminal.
Time required to obtain valid data out from SO following the rise of SCLK with 200 pF load.
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