![](http://datasheet.mmic.net.cn/370000/P9S12XEP100J1VVLR_datasheet_16728329/P9S12XEP100J1VVLR_362.png)
Chapter 10 XGATE (S12XGATEV3)
MC9S12XE-Family Reference Manual , Rev. 1.07
362
Freescale Semiconductor
4
XGSS
XGATE Single Step
— This bit forces the execution of a single instruction.
1
Read:
0 No single step in progress
1 Single step in progress
Write
0 No effect
1 Execute a single RISC instruction
Note:
Invoking a Single Step will cause the XGATE to temporarily leave Debug Mode until the instruction has
been executed.
3
XGFACT
Fake XGATE Activity
— This bit forces the XGATE to flag activity to the MCU even when it is idle. When it is set
the MCU will never enter system stop mode which assures that peripheral modules will be clocked during XGATE
idle periods
Read:
0 XGATE will only flag activity if it is not idle or in debug mode.
1 XGATE will always signal activity to the MCU.
Write:
0 Only flag activity if not idle or in debug mode.
1 Always signal XGATE activity.
1
XGSWEF
XGATE Software Error Flag
— This bit signals a software error. It is set whenever the RISC core detects an
error condition
2
. The RISC core is stopped while this bit is set. Clearing this bit will terminate the current thread
and cause the XGATE to become idle.
Read:
0 No software error detected
1 Software error detected
Write:
0 No effect
1 Clears the XGSWEF bit
0
XGIE
XGATE Interrupt Enable
— This bit acts as a global interrupt enable for the XGATE module
Read:
0 All outgoing XGATE interrupts disabled (except software error interrupts)
1 All outgoing XGATE interrupts enabled
Write:
0 Disable all outgoing XGATE interrupts (except software error interrupts)
1 Enable all outgoing XGATE interrupts
1
Refer to
Section 10.6.1, “Debug Features
”
2
Refer to
Section 10.4.5, “Software Error Detection”
Table 10-1. XGMCTL Field Descriptions (Sheet 3 of 3)
Field
Description