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Chapter 8 S12X Debug (S12XDBGV3) Module
MC9S12XE-Family Reference Manual , Rev. 1.07
326
Freescale Semiconductor
8.3.2.8.8
Debug Comparator Data Low Mask Register (DBGXDLM)
Read: Anytime. See
Table 8-28
for visible register encoding.
Write: If DBG not armed. See
Table 8-28
for visible register encoding.
8.4
Functional Description
This section provides a complete functional description of the S12XDBG module. If the part is in secure
mode, the S12XDBG module can generate breakpoints but tracing is not possible.
8.4.1
S12XDBG Operation
Arming the S12XDBG module by setting ARM in DBGC1 allows triggering, and storing of data in the
tracebufferandcanbeusedtocausebreakpointstotheCPU12XortheXGATEmodule.TheDBGmodule
is made up of four main blocks, the comparators, control logic, the state sequencer, and the trace buffer.
The comparators monitor the bus activity of the CPU12X and XGATE. Comparators can be configured to
monitor address and databus. Comparators can also be configured to mask out individual data bus bits
during a compare and to use R/W and word/byte access qualification in the comparison. When a match
with a comparator register value occurs the associated control logic can trigger the state sequencer to
another state (see
Figure 8-22
). Either forced or tagged triggers are possible. Using a forced trigger, the
trigger is generated immediately on a comparator match. Using a tagged trigger, at a comparator match,
the instruction opcode is tagged and only if the instruction reaches the execution stage of the instruction
queue is a trigger generated. In the case of a transition to Final State, bus tracing is triggered and/or a
breakpoint can be generated. Tracing of both CPU12X and/or XGATE bus activity is possible.
Independent of the state sequencer, a breakpoint can be triggered by the external TAGHI / TAGLO signals
or by an XGATE S/W breakpoint request or by writing to the TRIG bit in the DBGC1 control register.
The trace buffer is visible through a 2-byte window in the register address map and can be read out using
standard 16-bit word reads.
Address: 0x002F
7
6
5
4
3
2
1
0
R
W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Reset
0
0
0
0
0
0
0
0
Figure 8-21. Debug Comparator Data Low Mask Register (DBGXDLM)
Table 8-37. DBGXDLM Field Descriptions
Field
Description
7–0
Bits[7:0]
Comparator Data Low Mask Bits
— The Comparator data low mask bits control whether the selected
comparator compares the data bus bits [7:0] to the corresponding comparator data compare bits. This register
is available only for comparators A and C.
0 Do not compare corresponding data bit
1 Compare corresponding data bit