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Chapter 5 External Bus Interface (S12XEBIV4)
MC9S12XE-Family Reference Manual , Rev. 1.07
250
Freescale Semiconductor
5.4.2.2
Instruction Queue Status Signals (IQSTAT)
The CPU instruction queue status (execution-start and data-movement information) is brought out as
IQSTAT[3:0] signals. For decoding of the IQSTAT values, refer to the S12X_CPU section.
5.4.2.3
Internal Visibility Data (IVD)
Dependingontheaccesssizeandalignment,eitherawordofreaddataismadevisibleontheaddresslines
or only the related data byte will be presented in the ECLK low phase. For details refer to
Table 5-10
.
Invalid IVD are brought out in case of non-CPU read accesses.
5.4.2.4
Emulation Modes Timing
A bus access lasts 1 ECLK cycle. In case of a stretched external access (emulation expanded mode), up to
an infinite amount of ECLK cycles may be added. ADDRx values will only be shown in ECLK high
phases, while ACCx, IQSTATx, and IVDx values will only be presented in ECLK low phases.
Based on this multiplex timing, ACCx are only shown in the current (first) access cycle. IQSTATx and
(for read accesses) IVDx follow in the next cycle. If the access takes more than one bus cycle, ACCx
display NULL (0x000) in the second and all following cycles of the access. IQSTATx display NULL
(0x0000) from the third until one cycle after the access to indicate continuation.
The resulting timing pattern of the external bus signals is outlined in the following tables for read, write
andinterleavedread/writeaccesses.Threeexamplesrepresentdifferentaccesslengthsof1,2,andn–1bus
cycles. Non-shaded bold entries denote all values related to Access #0.
011
XGATE PRR access
No access
1
100
101
CPU access error
110, 111
Reserved
1
Denotes also CPU accesses to BDM firmware and BDM registers (IQSTATx
are ‘XXXX’ and RW = 1 in these cases)
Table 5-10. IVD Read Data Output
Access
IVD[15:8]
IVD[7:0]
Word read of data at an even and even+1 address
ivd(even)
ivd(even+1)
Word read of data at an odd and odd+1 internal RAM address (misaligned)
ivd(odd+1)
ivd(odd)
Byte read of data at an even address
ivd(even)
addr[7:0] (rep.)
Byte read of data at an odd address
addr[15:8] (rep.)
ivd(odd)
Table 5-9. Determining Access Source from Control Signals
ACC[2:0]
Access Description