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參數(shù)資料
| 型號(hào)： | P87C380 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器) |
| 中文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42 |
| 文件頁數(shù)： | 64/84頁 |
| 文件大?。?/td> | 420K |
| 代理商： | P87C380 |
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1997 Dec 12
64
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
19.3
System operation
After a successful power-on reset, the P83C880 will
automatically start the mode detection and sync
separation by default. The output pulses of HSYNC and
VSYNC are delivered in the free running format by the
default setting. Since it takes at least 5 frames to finalize
the calculation of the HSYNC period, Hper, VSYNC period
and Vper, it is better to wait until the stable state is reached
to get the complete information after power-on reset.
Accordingly, Hpol, Vpol, Hpres, Vpres and sync separation
will be decided upon after Hper and Vper are settled. To
prevent interfering the CPU too often, the interrupt request
flag IE0 (SFR TCON) is only set if the mode (including
frequency or polarity) is changed. IE0 will be cleared either
by the CPU when the service routine is called (IT0 = 1) or
by the service routine itself (IT0 = 0).
If it is required to reduce power dissipation or if it is
preferred to stabilize the entire system after power-on
reset before mode detection is proceeded, the bit MARCH
(SFR MDCST) can be cleared to logic 0. Mode detection
can be activated at the desired moment later on by setting
MARCH to a logic 1.
In fact, the detection of the Device Power Management
Signalling (DPMS) modes like ‘Normal’, ‘Standby’,
‘Suspend’, ‘Power off’, etc. and sync separation are mixed
together with the display mode detection.
The mode detection function provides the hardware
vehicle to facilitate the mode detection and related
activities. Nevertheless, to use this facility to a maximum,
the proper interaction between software and hardware is
still essential. When VSYNC is absent and HSYNC is
present, the polarity of HSYNC is always fixed. A software
flow chart example is illustrated in Fig.32.
19.3.1
D
ISPLAY
P
OWER
M
ANAGEMENT
S
IGNALLING
(DPMS)
SPECIFICATION
According to the DPMS specification: Hfreq <10 kHz and
Vfreq <10 Hz indicates that HSYNC and VSYNC are
inactive. However, in the real application, there are no
modes running with 10 kHz
≤
Hfreq
≤
15 kHz and
10 Hz
≤
Vfreq
≤
40 Hz. Therefore, Hfreq = 15 kHz and
Vfreq = 40 Hz are chosen as the threshold to indicate an
active or inactive signal for HSYNC and VSYNC
respectively.
相關(guān)PDF資料 |
PDF描述 |
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| P83C880 | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器) |
| P83C180 | Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器) |
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| P83C570AAR | Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
| P83C570 | Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC |
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