參數(shù)資料
型號(hào)： P87C380
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器)
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件頁數(shù)： 13/84頁
文件大?。?/td> 420K
代理商： P87C380
1997 Dec 12
13
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
7.3.1
RAM B
UFFER
I/O I
NTERFACE
R
EGISTER
(RAMBUF)
RAMBUF is used as an I/O interface to the RAM buffer. If it is associated with the address pointer DDCADR which is
equipped with the capability of post increment, then it will be convenient to transfer the consecutive data stream. This
feature is useful to support the DDC/EDID data transfer.
Table 5
RAM Buffer I/O Interface Register (SFR address 9CH)
Table 6
Description of RAMBUF bits
7.3.2
M
ISCELLANEOUS
C
ONTROL
R
EGISTER
(DFCON)
This register is bit-addressable.
Table 7
Miscellaneous Control Register (SFR address C0H)
Table 8
Description of DFCON bits
7
6
5
4
3
2
1
0
RAMBUF.7
RAMBUF.6
RAMBUF.5
RAMBUF.4
RAMBUF.3
RAMBUF.2
RAMBUF.1
RAMBUF.0
BIT
SYMBOL
DESCRIPTION
7 to 0
RAMBUF.7 to RAMBUF.0
8-bit data which is read from or to be written into RAM buffer
7
6
5
4
3
2
1
0
EW2
SOGE
SYNCE
DDCE
S1E
ADCE
P14LVL
P8LVL
BIT
SYMBOL
DESCRIPTION
7
EW2
Watchdog Timer enable flag
. This flag is associated with the flags, EW1 (SFR
PWM10H) and EW0 in (SFR PWM10L) to form the enable/disable control key for the
Watchdog Timer (see Chapter 9). The Watchdog Timer is only disabled by
EW2 to EW0 = 101, else it is kept enabled for the rest of the combinations.
CSYNC
in
enable for pin CSYNC
in
/P1.6
. If SOGE = 1, the pin function is CSYNC
in
. If
SOGE = 0, the pin function is I/O port P1.6.
Sync separated signals output enable
for pins VSYNC
out
/P1.4 and HSYNC
out
/P1.5.
If SYNCE = 1, the pins function as VSYNC
out
and HSYNC
out
respectively.
If SYNCE = 0, the pins function as I/O ports P1.4 and P1.5 respectively.
Enable for DDC interface pins SCL1/P1.2 and SDA1/P1.3
. If DDCE = 1, the pins
function as SCL1 and SDA1 respectively for the DDC interface. If DDCE = 0, the pins
function as I/O ports P1.2 and P1.3 respectively.
Enable for I
2
C-bus interface pins SCL/P1.0 and SDA/P1.1
. If S1E = 1, the pins
function as SCL and SDA respectively for the I
2
C-bus
interface. If S1E = 0, the pins
function as I/O ports P1.0 and P1.1 respectively.
6
SOGE
5
SYNCE
4
DDCE
3
S1E
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