參數(shù)資料
型號(hào)： P87C380
廠商： NXP SEMICONDUCTORS
元件分類： 微控制器/微處理器
英文描述： Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器)
中文描述： 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, PLASTIC, SOT-270-1, SDIP-42
文件頁(yè)數(shù)： 50/84頁(yè)
文件大?。?/td> 420K
代理商： P87C380
1997 Dec 12
50
Philips Semiconductors
Product specification
Microcontrollers for monitors with DDC
interface, auto-sync detection and sync proc.
P83Cx80; P87C380
17.6
RAM buffer for the system and DDC application
The architecture of the RAM buffer is set up in a flexible configuration to use the RAM resource to a maximum. In principle
the RAM buffer can be shared as system or DDC RAM buffer. The relationship among those applications is arranged as
shown in Table 42.
Table 42
Relation between system RAM and DDC RAM
Notes
1.
Read/write through MOVX instruction might conflict with the access from DDC1 hardware. So the access from CPU
by using MOVX instruction is forbidden.
READ/WRITE through DDCADR and RAMBUF registers has the conflicting problem also. Even the content of
DDCADR, which should be employed by DDC1 hardware, will be damaged. So it is inhibited to use this type of
access.
If DDCADR reaches 127 it will automatically wrap around to 0 after the access is done.
The access conflict can be avoided because DDC1 access is done by the interrupt service routine. However, the
EDID transferring from the RAM buffer should be finished within 40
μ
s.
If DDCADR reaches 255 it will automatically wrap around to 0 after the access is done.
2.
3.
4.
5.
18 I
2
C-BUS INTERFACE
The P83C880 has a software I
2
C-bus interface that can be used in master mode. Full details of the I
2
C-bus are given in
the 80C51 family “Data Handbook IC20”and/or the document “The I
2
C-bus and how to use it”(ordering number
9398 393 40011).
The I
2
C-bus interface lines SDA and SCL share the same pins as Port 1 lines P1.1 and P1.0 respectively; selection is
done via the S1E bit in SFR DFCON (address C0H).
MODE
EX_DAT SWENB
AUX RAM 0 TO 127
AUX RAM 128 TO 255
NORMALLY
RESERVED FOR
NOTE
NORMALLY
RESERVED FOR
AVAILABLE
FOR
NOTE
DDC1
0
0
1
1
0
1
0
1
0
1
1
1
DDC1 EDID data
1, 2 and 3
3 and 4
1 and 2
4
3
system access
2
1, 2 and 5
4 and 5
5
DDC1 EDID data
DDC2
DDC2 EDID data
DDC2 EDID data
system access
相關(guān)PDF資料
PDF描述
P83C880 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器)
P83C180 Microcontrollers for monitors with DDC interface, auto-sync detection and sync proc(帶DDC接口，同步監(jiān)測(cè)和同步處理的監(jiān)視器微控制器)
P83C370AAR Microcontrollers for PAL/SECAM TV with OSD and VST(帶 OSD和 VST的在PAL/SECAM TV中應(yīng)用的微控制器)
P83C570AAR Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC
P83C570 Microcontrollers for NTSC TVs with On-Screen Display OSD and Closed Caption CC
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