Chapter 23 DQ256 Port Integration Module (S12XDQ256PIMV2)
MC9S12XDP512 Data Sheet, Rev. 2.17
922
Freescale Semiconductor
23.0.5.4
Port B Data Direction Register (DDRB)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
23.0.5.5
Port C Data Register (PORTC)
Read: Anytime. In emulation modes, read operations will return the data from the external bus, in all other
modes the data source is depending on the data direction value.
Write: Anytime. In emulation modes, write operations will also be directed to the external bus.
Table 23-6. DDRA Field Descriptions
Field
Description
7–0
DDRA[7:0]
Data Direction Port A — This register controls the data direction for port A. When Port A is operating as a general
purpose I/O port, DDRA determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note:
Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTA after changing the DDRA register.
7
6
5
4
3
2
1
0
R
DDRB7
DDRB6
DDRB5
DDRB4
DDRB3
DDRB2
DDRB1
DDRB0
W
Reset
0
0
0
0
0
0
0
0
Figure 23-6. Port B Data Direction Register (DDRB)
Table 23-7. DDRB Field Descriptions
Field
Description
7–0
DDRB[7:0]
Data Direction Port B — This register controls the data direction for port B. When Port B is operating as a general
purpose I/O port, DDRB determines whether each pin is an input or output. A logic level “1” causes the
associated port pin to be an output and a logic level “0” causes the associated pin to be a high-impedance input.
0 Associated pin is configured as input.
1 Associated pin is configured as output.
Note:
Due to internal synchronization circuits, it can take up to 2 bus clock cycles until the correct value is read
on PORTB after changing the DDRB register.
7
6
5
4
3
2
1
0
R
PC7
PC6
PC5
PC4
PC3
PC2
PC1
PC0
W
Reset
0
0
0
0
0
0
0
0
Figure 23-7. Port C Data Register (PORTC)