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參數(shù)資料
| 型號(hào)： | OZ6933 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | ACPI CardBus Controller |
| 中文描述： | ACPI的CardBus控制器 |
| 文件頁數(shù)： | 5/15頁 |
| 文件大?。?/td> | 126K |
| 代理商： | OZ6933 |
OZ6933
OZ6933-SF-1.7
Page 5
PIN LIST
Bold Text =
Normal Default Pin Name
PCI Bus Interface Pins
Pin Number
TQFP
4-5, 7-12, 16-
20, 22-24, 38-
43, 45-46, 48-
49, 51-56
Pin Name
Description
BGA
Input
Type
Power
Rail
Drive
AD[31:0]
PCI Bus Address Input/Data:
These
pins connect to PCI bus signals AD[31:0].
A Bus transaction consists of an address
phase followed by one or more data
phases.
E1, E2, F3, F1,
G5, H6, G3,
G2, H2, H1, J1,
J2, J3, J6, K1,
K2, M5, N2,
N1, N3, N6, P1,
P3, N5, P6, R2,
R3, T1, W4,
R6, U5, P7
G1, K3, M3, R1
TTL
I/O
4
PCI Spec
C/BE[3:0]#
PCI Bus Command/Byte Enable:
The
command signaling and byte enables are
multiplexed on the same pins. During the
address
phase
of
C/BE[3:0]# are interpreted as the bus
commands. During the data phase,
C/BE[3:0]#
are
interpreted
enables. The byte enables are to be valid
for the entirety of each data phase, and
they indicate which bytes in the 32-bit data
path are to carry meaningful data for the
current data phase.
Cycle Frame:
This input indicates to the
OZ6933 that a bus transaction is
beginning. While FRAME# is asserted,
data transfers continue. When FRAME#
is de-asserted, the transaction is in its final
phases.
Initiator Ready:
This input indicates the
initiating agent
’
s ability to complete the
current data phase of the transaction.
IRDY# is used in conjunction with TRDY#.
Target Ready:
This output indicates
target Agent
’
s the OZ6933
’
s ability to
complete the current data phase of the
transaction. TRDY# is used in conjunction
with IRDY#.
Stop:
This output indicates the current
target is requesting the master to stop the
current transaction.
Initialization Device Select:
This input is
used as chip select during configuration
read and write transactions. This is a
point-to-point signal. IDSEL can be used
as a chip select during configuration read
and write transactions.
Device Select:
This output is driven
active LOW when the PCI address is
recognized as supported, thereby acting
as the target for the current PCI cycle.
The Target must respond before timeout
occurs or the cycle will terminate.
Parity Error:
The output is driven active
LOW when a data parity error is detected
during a write phase.
a
transaction,
as
byte
13, 25, 36, 47
TTL
I/O
4
-
FRAME#
27
K6
TTL
I/O
4
-
IRDY#
29
L1
TTL
I/O
4
-
TRDY#
30
L2
TTL
I/O
4
PCI Spec
STOP#
32
L5
TTL
I/O
4
PCI Spec
IDSEL
15
H5
TTL
I
4
-
DEVSEL#
31
L3
TTL
I/O
4
PCI Spec
PERR#
33
L6
-
TO
4
PCI Spec
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