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參數(shù)資料
| 型號(hào)： | OX16C954 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 37/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954 |
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Data Sheet Revision 1.0
Page 37
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
15 A
DDITIONAL
F
EATURES
15.1 Additional Status Register ‘ASR’
ASR[0]: Transmitter disabled
logic 0
The transmtter is not disabled by in-band flow
control.
logic 1
The receiver has detected an XOFF, and has
disabled the transmtter.
This bit is cleared after a hardware reset or channel
software reset. The software driver may write a 0 to this bit
to re-enable the transmtter if it was disabled by in-band
flow control. Writing a 1 to this bit has no effect.
ASR[1]: Remote transmitter disabled
logic 0
The remote transmtter is not disabled by in-
band flow control.
logic 1
The transmtter has sent an XOFF character, to
disable the remote transmtter (cleared when
subsequent XON is sent).
This bit is cleared after a hardware reset or channel
software reset. The software driver may write a 0 to this bit
to re-enable the remote transmtter (an XON is
transmtted). Note: writing a 1 to this bit has no effect.
Note:
The remaining bits (ASR[7:2]) are read-only.
ASR[2]: RTS
This is the complement of the actual state of the RTS#pin
when the device is not in loopback mode. The driver
software can determne if the remote transmtter is disabled
by RTS#out-of-band flow control by reading this bit. In
loopback mode this bit reflects the flow control status rather
than the pins actual state.
ASR[3]: DTR
This is the complement of the actual state of the DTR#pin
when the device is not in loopback mode. The driver
software can determne if the remote transmtter is disabled
by DTR#out-of-band flow control by reading this bit. In
loopback mode this bit reflects the flow control status rather
than the pins actual state.
ASR[4]: Special character detected
logic 0
No special character has been detected.
logic 1
A special character has been received and is
stored in the RHR.
This can be used to determne whether a level 5 interrupt
was caused by receiving a special character rather than an
XOFF. The flag is cleared following the read of the ASR.
ASR[5]: FIFOSEL
This bit reflects the unlatched state of the FIFOSEL pin.
ASR[6]: FIFO size
logic 0
FIFOs are 16 deep if FCR[0] = 1.
logic 1
FIFOs are 128 deep if FCR[0] = 1.
Note: If FCR[0] = 0, the FIFOs are 1 deep.
ASR[7]: Transmitter Idle
logic 0
Transmtter is transmtting.
logic 1
Transmtter is idle.
This bit reflects the state of the internal transmtter. It is set
when both the transmtter FIFO and shift register are
empty.
15.2 FIFO Fill levels ‘TFL & RFL’
The number of characters stored in the THR and RHR can
be determned by reading the TFL and RFL registers
respectively. As the UART clock is asynchronous with
respect to the processor, it is possible for the levels to
change during a read of these FIFO levels. It is therefore
recommended that the levels are read twice and compared
to check that the values obtained are valid. The values
should be interpreted as follows:
1. The number of characters in the THR is no greater
than the value read back fromTFL.
2. The number of characters in the RHR is no less than
the value read back fromRFL.
15.3 Additional Control Register ‘ACR’
The ACR register is located at offset 0x00 of the ICR
ACR[0]: Receiver disable
logic 0
The receiver is enabled, receiving data and
storing it in the RHR.
logic 1
The receiver is disabled. The receiver
continues to operate as normal to maintain the
framng synchronisation with the receive data
streambut received data is not stored into the
RHR. In-band flow control characters continue
to be detected and acted upon. Special
characters will not be detected.
Changes to this bit will only be recognised following the
completion of any data reception pending.
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