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參數(shù)資料
| 型號： | OX16C954 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | High Performance Quad UART with 128-byte FIFOs Intel / Motorola Bus Interface |
| 中文描述： | UART的高性能四路128字節(jié)的FIFO英特爾/摩托羅拉總線接口 |
| 文件頁數(shù)： | 20/54頁 |
| 文件大?。?/td> | 529K |
| 代理商： | OX16C954 |
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Data Sheet Revision 1.0
Page 20
OX16C954 rev B
OXFORD SEMICONDUCTOR LTD.
Register
Name
SPR
Offset
10
R/W
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Indexed Control Register Set
ICR
Read
Enable
Level
Enable
ACR
0x00
R/W
Addit-
ional
Status
Enable
950
Trigger
DTR definition and
control
Auto
DSR
Flow
Control
Enable
Tx
Disable
Rx
Disable
CPR
0x01
R/W
5 Bit “integer” part of
clock prescaler
Unused
3 Bit “fractional” part of
clock prescaler
4 Bit N-times clock
selection bits [3:0]
Unused
TCR
0x02
R/W
CKS
0x03
R/W
Tx 1x
Mode
Unused
Tx CLK
Select
BDOUT
on DTR
DTR 1x
Tx CLK
Rx 1x
Mode
Receiver
Clock Sel[1:0]
TTL
0x04
R/W
Transmtter Interrupt Trigger Level (0-127)
RTL
0x05
R/W
Unused
Receiver Interrupt Trigger Level (1-127)
FCL
0x06
R/W
Unused
Automatic Flow Control Lower Trigger Level (0-127)
FCH
0x07
R/W
Unused
Automatic Flow Control Higher Trigger level (1-127)
ID1
0x08
R
Hardwired ID byte 1 (0x16)
ID2
0x09
R
Hardwired ID byte 1 (0xC9)
ID3
0x0A
R
Hardwired ID byte 1 (0x54)
REV
0x0B
R
Hardwired revision byte (0x04)
CSR
0x0C
W
Writing 0x00 to this register will
reset the UART (Except the CKS and CKA registers)
9
th
Bit
SChar 4
SChar 3
Reserved
NMR
0x0D
R/W
Unused
9
th
Bit
9
th
Bit
SChar 2
DCD
Wakeup
disable
FCR[3]
9
th
Bit
SChar 1
Trailing
RI edge
disable
FCR[2]
9
th
-bit Int.
En.
DSR
Wakeup
disable
FCR[1]
9 Bit
Enable
CTS
Wakeup
disable
FCR[0]
Good
Data
Status
RxRdy
status
( R )
MDM
0x0E
R/W
RFC
GDS
0X0F
0X10
R
R
FCR[7]
FCR[6]
FCR[5]
FCR[4]
Unused
DMS
0x11
R/W
Force
TxRdy
inactive
Force
RxRdy
inactive
Unused
TxRdy
status
( R )
PIDX
CKA
0x12
0x13
R
Hardwired Port Index ( 0x00, 0x01, 0x02, 0x03 respectively )
Unused
R/W
Use
CLKSEL
pin for
sys-clk
Invert
DTR
signal
Invert
internal
tx clock
Invert
internal
rx clock
Table 7: Indexed Control Register Set
Note 10:
Offset values not listed in the table are reserved for future use and must not be used.
The SPR offset column indicates the value that must be written into SPR prior to reading / writing any of the Indexed Control Registers via ICR.
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