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參數(shù)資料
| 型號： | OR2T40B |
| 廠商： | Lattice Semiconductor Corporation |
| 元件分類： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場可編程門陣列 |
| 文件頁數(shù)： | 66/192頁 |
| 文件大?。?/td> | 935K |
| 代理商： | OR2T40B |
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Data Sheet
January 2002
ORCA
Series 2 FPGAs
66
Lattice Semiconductor
Pin Information
Pin Descriptions
This section describes the pins found on the Series 2 FPGAs. Any pin not described in this table is a user-program-
mable I/O. During con
fi
guration, the user-programmable I/Os are 3-stated with an internal pull-up resistor enabled.
Table 17. Pin Descriptions
Symbol
I/O
Description
Dedicated Pins
V
DD
GND
I/O-V
DD
5
—
—
—
Positive power supply.
Ground supply.
5 V tolerant select. (For 2TxxA only.) All V
DD
5 pins must be tied to either the 5 V power
supply if 5 V tolerant I/O buffers are to be used, or to the 3.3 V power supply (V
DD
) if
they are not. For 2CxxA and 2TxxB devices, these pins are user-programmable I/Os.
During con
fi
guration, RESET forces the restart of con
fi
guration and a pull-up is
enabled. After con
fi
guration, RESET can be used as a general FPGA input or as a
direct input, which causes all PLC latches/FFs to be asynchronously set/reset.
In the master and asynchronous peripheral modes, CCLK is an output which strobes
con
fi
guration data in. In the slave or synchronous peripheral mode, CCLK is input syn-
chronous with the data on DIN or D[7:0].
DONE is a bidirectional pin with an optional pull-up resistor. As an active-high, open-
drain output, a high-level on this signal indicates that con
fi
guration is complete. As an
input, a low level on DONE delays FPGA start-up after con
fi
guration*.
PRGM is an active-low input that forces the restart of con
fi
guration and resets the
boundary-scan circuitry. This pin always has an active pull-up.
This pin must be held high during device initialization until the
INIT
pin goes high.
RESET
I
CCLK
I
DONE
I/O
PRGM
I
RD_CFG
I
This pin always has an active pullup.
During con
fi
guration,
RD_CFG
is an active-low input that activates the TS_ALL function
and 3-states all of the I/O.
After con
fi
guration,
RD_CFG
can be selected (via a bit stream option) to activate the
TS_ALL function as described above, or, if readback is enabled via a bit stream option,
a high-to-low transition on
RD_CFG
will initiate readback of the con
fi
guration data,
including PFU output states, starting with frame address 0.
RD_DATA/TDO is a dual-function pin. If used for readback, RD_DATA provides con gu-
ration data out. If used in boundary scan, TDO is test data out.
Special-Purpose Pins (Become User I/O After Configuration)
RDY/RCLK
O
During con
fi
guration in peripheral mode, RDY indicates another byte can be written to
the FPGA. If a read operation is done when the device is selected, the same status is
also available on D7 in asynchronous peripheral mode. After con
fi
guration, the pin is a
user-programmable I/O*.
During the master parallel con
fi
guration mode RCLK, which is a read output signal to an
external memory. This output is not normally used. After con
fi
guration, this pin is a user-
programmable I/O pin*.
DIN
I
During slave serial or master serial con
fi
guration modes, DIN accepts serial con
fi
gura-
tion data synchronous with CCLK. During parallel con
fi
guration modes, DIN is the D0
input. During con
fi
guration, a pull-up is enabled, and after con
fi
guration, this pin is a
user-programmable I/O pin*.
RD_DATA/TDO
O
* The FPGA States of Operation section contains more information on how to control these signals during start-up. The timing of DONE
release is controlled by one set of bit stream options, and the timing of the simultaneous release of all other con
fi
guration pins (and the acti-
vation of all user I/Os) is controlled by a second set of options.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| OR2T40B7BA352-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T40B7BA352I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T40B7BC352-DB | 制造商:Rochester Electronics LLC 功能描述:- Bulk |
| OR2T40B7BC432-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
| OR2T40B7BC432I-DB | 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風格:SMD/SMT 封裝 / 箱體:FBGA-256 |
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