參數(shù)資料
型號： OR2T40B
廠商： Lattice Semiconductor Corporation
元件分類： FPGA
英文描述： Field-Programmable Gate Arrays
中文描述： 現(xiàn)場可編程門陣列
文件頁數(shù)： 52/192頁
文件大?。?/td> 935K
代理商： OR2T40B
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52
Lattice Semiconductor
Data Sheet
January 2002
ORCA
Series 2 FPGAs
Special Function Blocks
Special function blocks in the Series 2 provide extra
capabilities beyond general FPGA operation. These
blocks reside in the corners of the FPGA array.
Single Function Blocks
Most of the special function blocks perform a speci
fi
c
dedicated function. These functions are data/con
fi
gura-
tion readback control, global 3-state control (TS_ALL),
internal oscillator generation, global set/reset (GSRN),
and start-up logic.
Readback Logic
The readback logic is located in the upper right corner
of the FPGA.
Readback is used to read back the con
fi
guration data
and, optionally, the state of the PFU outputs. A read-
back operation can be done while the FPGA is in nor-
mal system operation. The readback operation cannot
be daisy-chained. To use readback, the user selects
options in the bit stream generator in the
ORCA
Foundry Development System.
Table 11 provides readback options selected in the bit
stream generator tool. The table provides the number
of times that the con
fi
guration data can be read back.
This is intended primarily to give the user control over
the security of the FPGA’s con
fi
guration program. The
user can prohibit readback (0), allow a single readback
(1), or allow unrestricted readback (U).
Table 11. Readback Options
The pins used for readback are readback data
(RD_DATA), read con
fi
guration (
RD_CFG
), and con
fi
gu-
ration clock (CCLK). A readback operation is initiated
by a high-to-low transition on
RD_CFG
. The
RD_CFG
input must remain low during the readback operation.
The readback operation can be restarted at frame 0 by
driving the
RD_CFG
pin high, applying at least two ris-
ing edges of CCLK, and then driving
RD_CFG
low
again. One bit of data is shifted out on RD_DATA at the
rising edge of CCLK. The
fi
rst start bit of the readback
frame is transmitted out several cycles after the rst ris-
ing edge of CCLK after
RD_CFG
is input low (see Table
48, Readback Timing Characteristics in the Timing
Characteristics section).
It should be noted that the RD_DATA output pin is also
used as the dedicated boundary-scan output pin, TDO.
If this pin is being used as TDO, the RD_DATA output
from readback can be routed internally to any other pin
desired. The
RD_CFG
input pin is also used to control
the global 3-state (TS_ALL) function. Before and during
con
fi
guration, the TS_ALL signal is always driven by
the
RD_CFG
input and readback is disabled. After con-
fi
guration, the selection as to whether this input drives
the readback or global 3-state function is determined
by a set of bit stream options. If used as the
RD_CFG
input for readback, the internal TS_ALL input can be
routed internally to be driven by any input pin.
The readback frame contains the con
fi
guration data
and the state of the internal logic. During readback, the
value of all
fi
ve PFU outputs can be captured. The fol-
lowing options are allowed when doing a capture of the
PFU outputs.
1. Do not capture data (the data written to the capture
RAMs, usually 0, will be read back).
2. Capture data upon entering readback.
3. Capture data based upon a con
fi
gurable signal
internal to the FPGA. If this signal is tied to
logic 0, capture RAMs are written continuously.
4. Capture data on either options 2 or 3 above.
The readback frame has a similar, but not identical, for-
mat to the con
fi
guration frame. This eases a bitwise
comparison between the con
fi
guration and readback
data. The readback data is not inverted. Every data
frame has one low start bit and one high stop bit. The
preamble, including the length count
fi
eld, is not part of
the readback frame. The readback frame contains
states in locations not used in the con
fi
guration. These
locations need to be masked out when comparing the
con
fi
guration and readback frames. The development
system optionally provides a readback bit stream to
compare to readback from the FPGA. Also note that if
any of the LUTs are used as RAM and new data is writ-
ten to them, these bits will not have the same values as
the original con
fi
guration data frame either.
Option
Function
0
1
U
Prohibit Readback
Allow One Readback Only
Allow Unrestricted Number of Readbacks
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參數(shù)描述
OR2T40B7BA352-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2T40B7BA352I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2T40B7BC352-DB 制造商:Rochester Electronics LLC 功能描述:- Bulk
OR2T40B7BC432-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
OR2T40B7BC432I-DB 功能描述:FPGA - 現(xiàn)場可編程門陣列 Use ECP/EC or XP RoHS:否 制造商:Altera Corporation 系列:Cyclone V E 柵極數(shù)量: 邏輯塊數(shù)量:943 內(nèi)嵌式塊RAM - EBR:1956 kbit 輸入/輸出端數(shù)量:128 最大工作頻率:800 MHz 工作電源電壓:1.1 V 最大工作溫度:+ 70 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:FBGA-256
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