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40
Lattice Semiconductor
Data Sheet
January 2002
ORCA
Series 2 FPGAs
FPGA States of Operation
Prior to becoming operational, the FPGA goes through a
sequence of states, including initialization, con
fi
guration,
and start-up. Figure 36 outlines these three FPGA
states.
5-4529(F).r6
Figure 36. FPGA States of Operation
Initialization
Upon powerup, the device goes through an initialization
process. First, an internal power-on-reset circuit is trig-
gered when power is applied. When V
DD
reaches the
voltage at which portions of the FPGA begin to operate
(2.5 V to 3 V for the OR2CxxA, 2.2 V to 2.7 V for the
OR2TxxA/OR2TxxB), the I/Os are con
fi
gured based on
the con
fi
guration mode, as determined by the mode
select inputs M[2:0]. A time-out delay is initiated when
V
DD
reaches between 3.0 V and 4.0 V (OR2CxxA) or
2.7 V to 3.0 V (OR2TxxA/2TxxB) to allow the power
supply voltage to stabilize. The INIT and DONE outputs
are low. At powerup, if V
DD
does not rise from 2.0 V to
V
DD
in less than 25 ms, the user should delay con
fi
gu-
ration by inputting a low into INIT, PRGM, or RESET
until V
DD
is greater than the recommended minimum
operating voltage (4.75 V for OR2CxxA commercial
devices and 3.0 V for OR2TxxA/B devices).
At the end of initialization, the default con
fi
guration
option is that the con
fi
guration RAM is written to a low
state. This prevents shorts prior to con
fi
guration. As a
con
fi
guration option, after the
fi
rst con
fi
guration (i.e., at
recon
fi
guration), the user can recon
fi
gure without
clearing the internal con
fi
guration RAM
fi
rst.
The active-low, open-drain initialization signal INIT is
released and must be pulled high by an external resis-
tor when initialization is complete. To synchronize the
con
fi
guration of multiple FPGAs, one or more INIT pins
should be wire-ANDed. If INIT is held low by one or
more FPGAs or an external device, the FPGA remains
in the initialization state. INIT can be used to signal that
the FPGAs are not yet initialized. After INIT goes high
for two internal clock cycles, the mode lines (M[3:0])
are sampled and the FPGA enters the con
fi
guration
state.
The high during con
fi
guration (HDC), low during con g-
uration (LDC), and DONE signals are active outputs in
the FPGA’s initialization and con
fi
guration states. HDC,
LDC, and DONE can be used to provide control of
external logic signals such as reset, bus enable, or
PROM enable during con
fi
guration. For parallel master
con
fi
guration modes, these signals provide PROM
enable control and allow the data pins to be shared
with user logic signals.
If con
fi
guration has begun, an assertion of RESET or
PRGM initiates an abort, returning the FPGA to the ini-
tialization state. The PRGM and RESET pins must be
pulled back high before the FPGA will enter the con g-
uration state. During the start-up and operating states,
only the assertion of PRGM causes a recon
fi
guration.
In the master con
fi
guration modes, the FPGA is the
source of con
fi
guration clock (CCLK). In this mode, the
initialization state is extended to ensure that, in daisy-
chain operation, all daisy-chained slave devices are
ready. Independent of differences in clock rates, master
mode devices remain in the initialization state an addi-
tional six internal clock cycles after INIT goes high.
When con
fi
guration is initiated, a counter in the FPGA
is set to 0 and begins to count con
fi
guration clock
cycles applied to the FPGA. As each con
fi
guration data
frame is supplied to the FPGA, it is internally assem-
bled into data words. Each data word is loaded into the
internal con
fi
guration memory. The con
fi
guration load-
ing process is complete when the internal length count
equals the loaded length count in the length count eld,
and the required end of con
fi
guration frame is written.
– ACTIVE I/O
– RELEASE INTERNAL RESET
– DONE GOES HIGH
START-UP
INITIALIZATION
CONFIGURATION
RESET
OR
PRGM
LOW
PRGM
LOW
– CLEAR CONFIGURATION MEMORY
– INIT LOW, HDC HIGH, LDC LOW
OPERATION
POWERUP
– POWER-ON TIME DELAY
– M[3:0] MODE IS SELECTED
– CONFIGURATION DATA FRAME WRITTEN
– INIT HIGH, HDC HIGH, LDC LOW
– DOUT ACTIVE
YES
NO
NO
RESET,
INIT,
OR
PRGM
LOW
BIT
ERROR
YES