參數(shù)資料
型號(hào): OR2T04A-4BC100
廠商: Electronic Theatre Controls, Inc.
元件分類: FPGA
英文描述: Field-Programmable Gate Arrays
中文描述: 現(xiàn)場(chǎng)可編程門陣列
文件頁(yè)數(shù): 68/192頁(yè)
文件大?。?/td> 3148K
代理商: OR2T04A-4BC100
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)當(dāng)前第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)第115頁(yè)第116頁(yè)第117頁(yè)第118頁(yè)第119頁(yè)第120頁(yè)第121頁(yè)第122頁(yè)第123頁(yè)第124頁(yè)第125頁(yè)第126頁(yè)第127頁(yè)第128頁(yè)第129頁(yè)第130頁(yè)第131頁(yè)第132頁(yè)第133頁(yè)第134頁(yè)第135頁(yè)第136頁(yè)第137頁(yè)第138頁(yè)第139頁(yè)第140頁(yè)第141頁(yè)第142頁(yè)第143頁(yè)第144頁(yè)第145頁(yè)第146頁(yè)第147頁(yè)第148頁(yè)第149頁(yè)第150頁(yè)第151頁(yè)第152頁(yè)第153頁(yè)第154頁(yè)第155頁(yè)第156頁(yè)第157頁(yè)第158頁(yè)第159頁(yè)第160頁(yè)第161頁(yè)第162頁(yè)第163頁(yè)第164頁(yè)第165頁(yè)第166頁(yè)第167頁(yè)第168頁(yè)第169頁(yè)第170頁(yè)第171頁(yè)第172頁(yè)第173頁(yè)第174頁(yè)第175頁(yè)第176頁(yè)第177頁(yè)第178頁(yè)第179頁(yè)第180頁(yè)第181頁(yè)第182頁(yè)第183頁(yè)第184頁(yè)第185頁(yè)第186頁(yè)第187頁(yè)第188頁(yè)第189頁(yè)第190頁(yè)第191頁(yè)第192頁(yè)
Data Sheet
June 1999
ORCA Series 2 FPGAs
68
Lucent Technologies Inc.
Pin Information
(continued)
Package Compatibility
The package pinouts are consistent across ORCA
Series FPGAs with the following exception:
some
user
I/O pins that do not have any special functions will
be converted to V
DD
5 pins for the OR2TxxA series
.
If the designer does not use these pins for the
OR2CxxA and OR2TxxB series, then pinout compati-
bility will be maintained between the ORCA OR2CxxA,
OR2TxxA, and OR2TxxB series of FPGAs. Note that
they must be connected to a power supply for the
OR2TxxA series.
Package pinouts being consistent across all ORCA
Series FPGAs enables a designer to select a package
based on I/O requirements and change the FPGA with-
out laying out the printed-circuit board again. The
change might be to a larger FPGA if additional func-
tionality is needed, or it might be to a smaller FPGA to
decrease unit cost.
Table 18A provides the number of user I/Os available
for the ORCA OR2CxxA and OR2TxxB Series FPGAs
for each available package, and Table 18B provides the
number of user I/Os available in the ORCAOR2TxxA
series. It should be noted that the number of user I/Os
available for the OR2TxxA series is reduced from the
equivalent OR2CxxA devices by the number of
required V
DD
5 pins, as shown in Table 18B. The pins
that are converted from user I/O to V
DD
5 are denoted
as I/O-V
DD
5 in the pin information tables (Table 19
through 28). Each package has six dedicated configu-
ration pins.
Table 19—Table 28. provide the package pin and pin
function for the ORCA Series 2 FPGAs and packages.
The bond pad name is identified in the PIC nomencla-
ture used in the ORCA Foundry design editor.
When the number of FPGA bond pads exceeds the
number of package pins, bond pads are unused. When
the number of package pins exceeds the number of
bond pads, package pins are left unconnected (no
connects). When a package pin is to be left as a no
connect for a specific die, it is indicated as a note in the
device pad column for the FPGA. The tables provide no
information on unused pads.
Table 18A. ORCAOR2CxxA and OR2TxxB Series FPGA I/Os Summary
* 432 EBGA not available for OR2T15B
Device
84-Pin
PLCC
100-Pin
TQFP
144-Pin
TQFP
160-Pin
QFP
208-Pin
SQFP/
SQFP2
240-Pin
SQFP/
SQFP2
256-Pin
PBGA
304-Pin
SQFP/
SQFP2
352-Pin
PBGA
432-Pin
EBGA
OR2C04A
User I/Os
V
DD
/V
SS
OR2C06A
User I/Os
V
DD
/V
SS
OR2C08A
User I/Os
V
DD
/V
SS
OR2C10A
User I/Os
V
DD
/V
SS
OR2C12A
User I/Os
V
DD
/V
SS
OR2C15A/OR2T15B
User I/Os
V
DD
/V
SS
OR2C26A
User I/Os
V
DD
/V
SS
OR2C40A/OR2T40B
User I/Os
V
DD
/V
SS
64
14
77
17
114
24
130
24
160
31
64
14
77
17
114
24
130
24
171
31
192
42
192
26
64
14
130
24
171
31
192
40
221
26
64
14
130
24
171
31
192
40
221
26
256
48
64
14
171
31
192
42
223
26
252
46
288
48
64
14
171
31
192
42
223
26
252
46
298
48
320*
84
171
31
192
42
252
46
298
48
342
84
171
31
192
42
252
46
342
84
相關(guān)PDF資料
PDF描述
OR2T04A-4BC100I Field-Programmable Gate Arrays
OR2T04A-4BC144 Field-Programmable Gate Arrays
OR2T04A-4BC144I Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1000pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Solder Coated SnPb; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate
OR2T04A-4BC160 Field-Programmable Gate Arrays
OR2T04A-4BC160I Field-Programmable Gate Arrays
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OR2T04A-4BC100I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
OR2T04A-4BC144 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
OR2T04A-4BC144I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
OR2T04A-4BC160 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays
OR2T04A-4BC160I 制造商:未知廠家 制造商全稱:未知廠家 功能描述:Field-Programmable Gate Arrays