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參數(shù)資料
| 型號(hào)： | OR2T04A-4BC100 |
| 廠商： | Electronic Theatre Controls, Inc. |
| 元件分類(lèi)： | FPGA |
| 英文描述： | Field-Programmable Gate Arrays |
| 中文描述： | 現(xiàn)場(chǎng)可編程門(mén)陣列 |
| 文件頁(yè)數(shù)： | 55/192頁(yè) |
| 文件大?。?/td> | 3148K |
| 代理商： | OR2T04A-4BC100 |
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Data Sheet
June 1999
ORCA Series 2 FPGAs
Lucent Technologies Inc.
55
Special Function Blocks
(continued)
5-4488(F)
Figure 48. Boundary-Scan Interface
V
DD
EPROM
PROGRAM
D[7:0]
OE
CE
A[17:0]
A[17:0]
D[7:0]
DONE
M2
M1
M0
DONE
HDC
LDC
RCLK
CCLK
DIN
DOUT
DOUT
DIN
CCLK
DONE
DOUT
INIT
INIT
INIT
CCLK
V
V
DD
OR
GND
PRGM
PRGM
M2
M1
M0
PRGM
M2
M1
M0
V
DD
V
DD
HDC
LDC
RCLK
HDC
LDC
RCLK
V
DD
ORCA
SERIES
FPGA
SLAVE #2
ORCA
SERIES
FPGA
MASTER
ORCA
SERIES
FPGA
SLAVE #1
The BSM also increases test throughput with a dedi-
cated automatic test-pattern generator and with com-
pression of the test response with a signature analysis
register. The PC-based boundary-scan test card/soft-
ware allows a user to quickly prototype a boundary-
scan test setup.
Boundary-Scan Instructions
The ORCA Series boundary-scan circuitry is used for
three mandatory IEEE1149.1 tests (EXTEST, SAM-
PLE/PRELOAD, BYPASS) and four ORCA-defined
instructions. The 3-bit wide instruction register sup-
ports the eight instructions listed in Table 12.
Table 12. Boundary-Scan Instructions
The external test (EXTEST) instruction allows the inter-
connections between ICs in a system to be tested for
opens and stuck-at faults. If an EXTEST instruction is
performed for the system shown in Figure 47, the con-
nections between U1 and U2 (shown by nets a, b, and
c) can be tested by driving a value onto the given nets
from one device and then determining whether the
same value is seen at the other device. This is deter-
mined by shifting 2 bits of data for each pin (one for the
output value and one for the 3-state value) through the
BSR until each one aligns to the appropriate pin.
Then, based upon the value of the 3-state signal, either
the I/O pad is driven to the value given in the BSR, or
the BSR is updated with the input value from the I/O
pad, which allows it to be shifted out TDO.
The SAMPLE instruction is useful for system debug-
ging and fault diagnosis by allowing the data at the
FPGA’s I/Os to be observed during normal operation.
The data for all of the I/Os is captured simultaneously
into the BSR, allowing them to be shifted-out TDO to
the test host. Since each I/O buffer in the PICs is bidi-
rectional, two pieces of data are captured for each I/O
pad: the value at the I/O pad and the value of the
3-state control signal.
Code
000
001
010
011
100
101
110
111
Instruction
EXTEST
PLC Scan Ring 1
RAM Write (RAM_W)
Reserved
SAMPLE/PRELOAD
PLC Scan Ring 2
RAM Read (RAM_R)
BYPASS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| OR2T04A-4BC100I | Field-Programmable Gate Arrays |
| OR2T04A-4BC144 | Field-Programmable Gate Arrays |
| OR2T04A-4BC144I | Ceramic Chip Capacitors / MIL-PRF-55681; Capacitance [nom]: 1000pF; Working Voltage (Vdc)[max]: 100V; Capacitance Tolerance: +/-1%; Dielectric: Multilayer Ceramic; Temperature Coefficient: C0G (NP0); Lead Style: Surface Mount Chip; Lead Dimensions: 1206; Termination: Solder Coated SnPb; Body Dimensions: 0.125" x 0.062" x 0.051"; Container: Bag; Features: MIL-PRF-55681: M Failure Rate |
| OR2T04A-4BC160 | Field-Programmable Gate Arrays |
| OR2T04A-4BC160I | Field-Programmable Gate Arrays |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| OR2T04A-4BC100I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-4BC144 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-4BC144I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-4BC160 | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
| OR2T04A-4BC160I | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Field-Programmable Gate Arrays |
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