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3
OPA685
SPECIFICATIONS: V
S
= +5V
R
F
= 348
, R
L
= 100
to V
S
/2, and G = +8
,
(Figure 3 for AC performance only), unless otherwise noted.
OPA685U, N
TYP
GUARANTEED
0
°
C to
70
°
C
(3)
–40
°
C to
+85
°
C
(3)
MIN/
MAX
LEVEL
(1)
TEST
PARAMETER
CONDITIONS
+25
°
C
+25
°
C
(2)
UNITS
AC PERFORMANCE (Figure 3)
Small-Signal Bandwidth (V
O
= 0.5Vp-p)
G = +1, R
F
= 511
G = +2, R
F
= 487
G = +8, R
F
= 348
G = +16, R
= 162
G = +2, V
< 0.5Vp-p, R
= 487
R
F
= 511
, V
O
< 0.5Vp-p
G = +8, V
= 2Vp-p
G = +8, 2V Step
G = +8, V
O
= 0.5V Step
G = +8, V
O
= 2V Step
G = +8, V
O
= 2V Step
G = +8, V
O
= 2V Step
G = +8, f = 10MHz, V
O
= 2Vp-p
R
L
= 100
to V
S
/2
R
L
≥
500
to V
S
/2
R
L
= 100
to V
S
/2
R
L
≥
500
to V
S
/2
f > 1MHz
f > 1MHz
f > 1MHz
600
450
350
250
140
0.4
350
1900
0.8
1.0
9
7
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/
μ
s
ns
ns
ns
ns
typ
min
typ
typ
min
max
typ
min
typ
typ
typ
typ
C
B
C
C
B
B
C
B
C
C
C
C
240
220
200
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large Signal Bandwidth
Slew Rate
Rise/Fall Time
80
1.0
70
1.5
60
1.5
1300
1200
1100
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd Harmonic
–60
–68
–58
–60
1.7
13
19
–54
–60
–51
–55
1.8
15
22
–53
–59
–50
–54
2.2
15
22
–52
–58
–50
–54
2.2
15
22
dBc
dBc
dBc
dBc
nV/
√
Hz
pA/
√
Hz
pA/
√
Hz
max
max
max
max
max
max
max
B
B
B
B
B
B
B
3rd Harmonic
Input Voltage Noise
Non-Inverting Input Current Noise
Inverting Input Current Noise
DC PERFORMANCE
(4)
Open-Loop Transimpedance Gain (Z
OL
)
Input Offset Voltage
Average Offset Voltage Drift
Non-Inverting Input Bias Current
Average Non-Inverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Least Positive Input Voltage
(5)
Most Positive Input Voltage
(5)
Common-Mode Rejection Ratio (CMRR)
Non-Inverting Input Impedance
Inverting Input Resistance (R
I
)
OUTPUT
Most Positive Output Voltage
V
O
= V
S
/2, R
L
= 100
to V
S
/2
V
CM
= V
S
/2
V
CM
= V
S
/2
V
CM
= V
S
/2
V
CM
= V
S
/2
V
CM
= V
S
/2
V
CM
= V
S
/2
40
±
1
25
±
3
23
±
3.5
12
±
120
–550
±
120
–550
20
±
4.0
15
±
150
–650
±
150
–650
k
mV
μ
V/
°
C
μ
A
nA/
°
C
μ
A
nA/
°
C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
+40
+110
±
50
±
100
1.7
3.3
54
87 || 2
23
1.8
3.2
48
1.9
3.1
47
2.0
3.0
47
V
V
dB
max
min
min
typ
typ
A
A
A
C
C
V
CM
= V
S
/2
k
|| pF
Open-Loop
No Load
4.1
4.0
0.9
1.0
90
–70
0.3
3.9
3.8
1.1
1.2
62
–45
3.7
3.6
1.3
1.4
60
–40
3.5
3.4
1.5
1.6
58
–38
V
V
V
V
min
min
max
max
min
min
typ
A
A
A
A
A
A
C
R
L
= 100
to V
S
/2
No Load
R
L
= 100
to V
S
/2
V
O
= V
S
/2
V
= V
/2
G = +2, f = 100kHz
Least Positive Output Voltage
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (Disable Low)
Power Down Supply Current (+V
S
)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS)
POWER SUPPLY
Specified Single-Supply Operating Voltage
Max Single-Supply Operating Voltage
Max Quiescent Current
Min Quiescent Current
Power Supply Rejection Ratio (–PSRR)
TEMPERATURE RANGE
Specification: U, N
Thermal Resistance,
θ
JA
U
SO-8
N
SOT23-6
mA
mA
V
DIS
= 0
–270
150
150
70
3
±
160
±
20
3.3
1.8
100
μ
A
ns
ns
dB
pF
mV
mV
V
V
μ
A
typ
typ
typ
typ
typ
typ
typ
min
max
typ
C
C
C
C
C
C
C
A
A
C
G = +8, 10MHz
G = +2, R
L
= 150
, V
IN
= V
S
/2
G = +2, R
L
= 150
, V
IN
= V
S
/2
3.5
1.7
3.6
1.6
3.7
1.5
V
DIS
= 0
5
V
V
typ
max
max
min
min
C
A
A
A
A
12
11.3
9.0
51
12
11.3
8.3
49
12
11.3
8.1
48
V
S
= +5V
V
= +5V
Input Referred
10.7
10.7
54
mA
mA
dB
–40 to +85
°
C
typ
C
Junction-to-Ambient
125
150
°
C/W
°
C/W
typ
typ
C
C
NOTES: (1) Test levels: (A) 100% tested at 25
°
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25
°
C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23
°
C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node.
V
CM
is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at
±
CMIR limits.