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參數(shù)資料
| 型號(hào)： | OPA685N |
| 英文描述： | Ultra-Wideband, Current-Feedback OPERATIONAL AMPLIFIER With Disable TM |
| 中文描述： | 超寬帶，電流反饋運(yùn)算放大器商標(biāo)使用禁用 |
| 文件頁數(shù)： | 27/28頁 |
| 文件大?。?/td> | 283K |
| 代理商： | OPA685N |
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OPA685
point, any further current pulled out of V
DIS
goes through
those diodes holding the emitter-base voltage of Q1 at
approximately zero volts. This shuts off the collector cur-
rent out of Q1, turning the amplifier off. The supply current
in the disable mode are only those required to operate the
circuit of Figure 18.
When disabled, the output and input nodes go to a high
impedance state. If the OPA685 is operating in a gain of +1,
this will show a very high impedance (3pF || 1M
) at the
output and exceptional signal isolation. If operating at a
gain greater than +1, the total feedback network resistance
(R
F
+ R
G
) will appear as the impedance looking back into
the output, but the circuit will still show very high forward
and reverse isolation. If configured as an inverting ampli-
fier, the input and output will be connected through the
feedback network resistance (R
F
+ R
G
), giving relatively
poor input to output isolation.
One key parameter in disable operation is the output glitch
when switching in and out of the disabled mode. Figure 19
shows these glitches for the circuit of Figure 1 with the
input signal set to 0V. The glitch waveform at the output pin
is plotted along with the DIS pin voltage.
described below. In no case should the maximum junction
temperature be allowed to exceed 175
°
C.
Operating junction temperature (T
J
) is given by T
A
+ P
D
θ
JA
.
The total internal power dissipation (P
D
) is the sum of quies-
cent power (P
DQ
) and additional power dissipated in the output
stage (P
DL
) to deliver load power. Quiescent power is simply
the specified no-load supply current times the total supply
voltage across the part. P
DL
will depend on the required output
signal and load. However, for a grounded resistive load, P
DL
would be at a maximum when the output is fixed at a voltage
equal to one-half of either supply voltage (for equal bipolar
supplies). Under this condition, P
DL
= V
S2
/(4 R
L
), where R
L
includes feedback network loading.
Note that it is the power in the output stage and not into the
load that determines internal power dissipation.
As an absolute worst-case example, compute the maximum
T
J
using an OPA685N (SOT23-6 package) in the circuit of
Figure 1 operating at the maximum specified ambient tem-
perature of +85
°
C and driving a grounded 100
load.
P
D
= 10V 13.5mA + 5
2
/(4 (100
|| 458
)) = 211mW
Maximum T
J
= +85
°
C + (0.21W 150
°
C/W) = 117
°
C
This maximum operating junction temperature is well below
most system level targets. Most applications will be lower
since an absolute worst-case output stage power was as-
sumed in this calculation.
BOARD LAYOUT GUIDELINES
Achieving optimum performance with a high frequency
amplifier like the OPA685 requires careful attention to
board layout parasitics and external component types. Rec-
ommendations that will optimize performance include:
a) Minimize parasitic capacitance to any AC ground for
all of the signal I/O pins.
Parasitic capacitance on the
output and inverting input pins can cause instability; on the
non-inverting input, it can react with the source impedance
to cause unintentional bandlimiting. To reduce unwanted
capacitance, a window around the signal I/O pins should be
opened in all of the ground and power planes around those
pins. Otherwise, ground and power planes should be unbro-
ken elsewhere on the board.
b) Minimize the distance (< 0.25") from the power
supply pins to high frequency 0.1
μ
F decoupling capaci-
tors.
At the device pins, the ground and power plane layout
should not be in close proximity to the signal I/O pins. Avoid
narrow power and ground traces to minimize inductance
between the pins and the decoupling capacitors. The power
supply connections should always be decoupled with these
capacitors. An optional supply-decoupling capacitor across
the two power supplies (for bipolar operation) will improve
2nd harmonic distortion performance. Larger (2.2
μ
F to
6.8
μ
F) decoupling capacitors, effective at lower frequency,
should also be used on the main supply pins. These may be
placed somewhat farther from the device and may be shared
among several devices in the same area of the PC board.
Time (10ns/div)
O
0.2V
4.8V
Output Voltage
(0V Input)
V
DIS
+300
+200
+100
0
–100
FIGURE 19. Disable/Enable Glitch.
The transition edge rate (dv/dt) of the DIS control line will
influence this glitch. For the plot of Figure 19, the edge rate
was reduced until no further reduction in glitch amplitude
was observed. This approximately 2V/ns maximum slew
rate may be achieved by adding a simple RC filter into the
V
DIS
pin from a higher speed logic line. If extremely fast
transition logic is used, a 2k
series resistor between the
logic gate and the V
DIS
input pin will provide adequate
bandlimiting using just the parasitic input capacitance on the
V
DIS
pin while still ensuring adequate logic level swing.
THERMAL ANALYSIS
The OPA685 does not require external heatsinking for most
applications. Maximum desired junction temperature will
set the maximum allowed internal power dissipation as
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