參數(shù)資料
型號： OPA685N
英文描述： Ultra-Wideband, Current-Feedback OPERATIONAL AMPLIFIER With Disable TM
中文描述： 超寬帶，電流反饋運算放大器商標(biāo)使用禁用
文件頁數(shù)： 2/28頁
文件大?。?/td> 283K
代理商： OPA685N
2
OPA685
SPECIFICATIONS: V
S
=
±
5V
R
F
= 402
, R
L
= 100
, and G = +8
,
(Figure 1 for AC performance only), unless otherwise noted.
OPA685U, N
TYP
GUARANTEED
0
°
C to
70
°
C
(3)
–40
°
C to
+85
°
C
(3)
MIN/
MAX
LEVEL
(1)
TEST
PARAMETER
CONDITIONS
+25
°
C
+25
°
C
(2)
UNITS
AC PERFORMANCE (Figure 1)
Small-Signal Bandwidth (V
O
= 0.5Vp-p)
G = +1, R
F
= 523
G = +2, R
F
= 511
G = +8, R
F
= 402
G = +16, R
= 249
G = +2, V
= 0.5Vp-p, R
=523
R
F
= 523
, V
O
= 0.5Vp-p
G = +8, V
O
= 4Vp-p
G = –8, V
O
= 4V Step
G = +8, V
O
= 4V Step
G = +8, V
O
= 0.5V Step
G = +8, V
O
= 4V Step
G = +8, V
O
= 2V Step
G = +8, V
O
= 2V Step
G = +8, f = 10MHz, V
O
= 2Vp-p
R
L
= 100
R
L
≥
500
R
L
= 100
R
≥
500
f > 1MHz
f > 1MHz
f > 1MHz
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
G = +2, NTSC, V
O
= 1.4Vp, R
L
= 150
1200
900
420
340
350
3
350
4200
2900
0.7
1.0
4
3
MHz
MHz
MHz
MHz
MHz
dB
MHz
V/
μ
s
V/
μ
s
ns
ns
ns
ns
typ
typ
min
typ
min
max
typ
min
min
typ
typ
typ
typ
C
C
B
C
B
B
C
B
B
C
C
C
C
360
350
320
Bandwidth for 0.1dB Gain Flatness
Peaking at a Gain of +1
Large Signal Bandwidth
Slew Rate
150
4.5
80
5
70
6.0
3000
2400
2500
2400
2200
2100
Rise/Fall Time
Settling Time to 0.02%
0.1%
Harmonic Distortion
2nd Harmonic
–66
–75
–90
–84
1.7
13
19
0.10
0.01
–59
–69
–83
–78
1.8
15
22
–56
–66
–77
–76
2.2
15
22
–53
–63
–74
–75
2.3
15
22
dBc
dBc
dBc
dBc
nV/
√
Hz
pA/
√
Hz
pA/
√
Hz
%
deg
max
max
max
max
max
max
max
typ
typ
B
B
B
B
B
B
B
C
C
3rd Harmonic
Input Voltage Noise
Non-Inverting Input Current Noise
Inverting Input Current Noise
Differential Gain
Differential Phase
DC PERFORMANCE
(4)
Open-Loop Transimpedance Gain (Z
OL
)
Input Offset Voltage
Average Offset Voltage Drift
Non-Inverting Input Bias Current
Average Non-Inverting Input Bias Current Drift
Inverting Input Bias Current
Average Inverting Input Bias Current Drift
INPUT
Common-Mode Input Range
(5)
(CMIR)
Common-Mode Rejection Ratio (CMRR)
Non-Inverting Input Impedance
Inverting Input Resistance (R
I
)
OUTPUT
Voltage Output Swing
V
O
= 0V, R
= 100
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
V
CM
= 0V
42
±
1.7
26
±
3.5
24
±
5
+35
±
100
–530
±
120
–500
23
±
7
+40
±
130
–570
±
150
–560
k
mV
μ
V/
°
C
μ
A
nA/
°
C
μ
A
nA
°
/C
min
max
max
max
max
max
max
A
A
B
A
B
A
B
+56
+90
±
10
±
100
±
3.4
54
87 || 2
19
±
3.2
49
±
3.1
48
±
3.0
48
V
dB
min
min
typ
typ
A
A
C
C
V
CM
= 0V
k
|| pF
Open-Loop
No Load
100
Load
V
O
= 0
V
= 0
G = +8, f = 100kHz
±
4.1
±
3.6
+130
–90
0.2
±
3.9
±
3.3
+90
–60
±
3.8
±
3.2
+75
–50
±
3.8
±
3.1
+70
–45
V
V
min
min
min
min
typ
A
A
A
A
C
Current Output, Sourcing
Current Output, Sinking
Closed-Loop Output Impedance
DISABLE (Disabled Low)
Power Down Supply Current (+V
S
)
Disable Time
Enable Time
Off Isolation
Output Capacitance in Disable
Turn On Glitch
Turn Off Glitch
Enable Voltage
Disable Voltage
Control Pin Input Bias Current (DIS)
POWER SUPPLY
Specified Operating Voltage
Maximum Operating Voltage Range
Max Quiescent Current
Min Quiescent Current
Power Supply Rejection Ratio (–PSRR)
TEMPERATURE RANGE
Specification: U, N
Thermal Resistance,
θ
JA
U
SO-8
N
SOT23-6
mA
mA
V
DIS
= 0
–320
100
100
70
3
±
160
±
20
3.3
1.8
115
μ
A
ns
ns
dB
pF
mV
mV
V
V
μ
A
typ
typ
typ
typ
typ
typ
typ
min
max
max
C
C
C
C
C
C
C
A
A
A
G = +8, 10MHz
G = +2, R
L
= 150
, V
IN
= 0
G = +2, R
L
= 150
, V
IN
= 0
3.5
1.7
160
3.6
1.6
160
3.7
1.5
160
V
DIS
= 0
±
5
V
V
typ
max
max
min
typ
C
A
A
A
A
±
6
13.5
12.5
49
±
6
13.5
11.9
47
±
6
13.5
11.2
46
V
S
=
±
5V
V
=
±
5V
Input Referred
12.9
12.9
55
mA
mA
dB
–40 to +85
°
C
typ
C
Junction-to-Ambient
125
150
°
C/W
°
C/W
typ
typ
C
C
NOTES: (1) Test levels: (A) 100% tested at 25
°
C. Over temperature limits by characterization and simulation. (B) Limits set by characterization and simulation.
(C) Typical value only for information. (2) Junction temperature = ambient for 25
°
C guaranteed specifications. (3) Junction temperature = ambient at low temperature
limit: junction temperature = ambient +23
°
C at high temperature limit for over temperature guaranteed specifications. (4) Current is considered positive out-of-node.
V
CM
is the input common-mode voltage. (5) Tested < 3dB below minimum specified CMRR at
±
CMIR limits.
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