參數(shù)資料
型號(hào)： OPA683IDBVR
元件分類： 運(yùn)動(dòng)控制電子
英文描述： OP-AMP|SINGLE|BIPOLAR|TSOP|6PIN|PLASTIC
中文描述： 運(yùn)放|單|雙極|的TSOP | 6針|塑料
文件頁(yè)數(shù)： 17/24頁(yè)
文件大?。?/td> 400K
代理商： OPA683IDBVR
OPA683
SBOS221B
17
www.ti.com
OUTPUT CURRENT AND VOLTAGE
The OPA683 provides output voltage and current capabilities
that can support the needs of driving doubly-terminated 50
lines. Changing the 1k
load in Figure 1 to a 100
will give
a total load that is the parallel combination of the 100
load
and the 2.4k
total feedback network impedance. This 96
load will require no more than 36mA output current to support
a
±
3.5V output voltage swing. This is within the specified
minimum output current of +58mA/
–
45mA over the full tem-
perature range.
The specifications described above, though familiar in the
industry, consider voltage and current limits separately. In
many applications, it is the voltage
current, or V-I product,
which is more relevant to circuit operation. Refer to the
“
Output Voltage and Current Limitations
”
plot in the Typical
Characteristics. The X and Y axes of this graph show the
zero-voltage output current limit and the zero-current output
voltage limit, respectively. The four quadrants give a more
detailed view of the OPA683
’
s output drive capabilities.
Superimposing resistor load lines onto the plot shows the
available output voltage and current for specific loads.
The minimum specified output voltage and current over
temperature are set by worst-case simulations at the cold
temperature extreme. Only at cold startup will the output
current and voltage decrease to the numbers shown in the
Electrical Specifications. As the output transistors deliver
power, their junction temperatures will increase, decreasing
their V
BE
’
s (increasing the available output voltage swing)
and increasing their current gains (increasing the available
output current). In steady state operation, the available
output voltage and current will always be greater than that
shown in the over-temperature specifications since the out-
put stage junction temperatures will be higher than the
minimum specified operating ambient.
To maintain maximum output stage linearity, no output short
circuit protection is provided. This will not normally be a
problem since most applications include a series matching
resistor at the output that will limit the internal power dissipa-
tion if the output side of this resistor is shorted to ground.
However, shorting the output pin directly to the adjacent
positive power-supply pin (8-pin packages) will, in most
cases, destroy the amplifier. If additional short-circuit protec-
tion is required, consider a small series resistor in the power-
supply leads. This will, under heavy output loads, reduce the
available output voltage swing. A 5
series resistor in each
power-supply lead will limit the internal power dissipation to
less than 1W for an output short circuit while decreasing the
available output voltage swing only 0.25V for up to 50mA
desired load currents. Always place the 0.1
μ
F power-supply
decoupling capacitors after these supply current limiting
resistors directly on the supply pins.
DRIVING CAPACITIVE LOADS
One of the most demanding and yet very common load
conditions for an op amp is capacitive loading. Often, the
capacitive load is the input of an ADC
—
including additional
external capacitance which may be recommended to im-
prove ADC linearity. A high-speed, high open-loop gain
amplifier like the OPA683 can be very susceptible to de-
creased stability and closed-loop response peaking when a
capacitive load is placed directly on the output pin. When the
amplifier
’
s open-loop output resistance is considered, this
capacitive load introduces an additional pole in the signal
path that can decrease the phase margin. Several external
solutions to this problem have been suggested. When the
primary considerations are frequency response flatness, pulse
response fidelity and/or distortion, the simplest and most
effective solution is to isolate the capacitive load from the
feedback loop by inserting a series isolation resistor between
the amplifier output and the capacitive load. This does not
eliminate the pole from the loop response, but rather shifts it
and adds a zero at a higher frequency. The additional zero
acts to cancel the phase lag from the capacitive load pole,
thus increasing the phase margin and improving stability.
The Typical Characteristics show the recommended
“
R
S
vs
Capacitive Load
”
and the resulting frequency response at the
load. The 1k
resistor shown in parallel with the load
capacitor is a measurement path and may be omitted.
Parasitic capacitive loads greater than 3pF can begin to
degrade the performance of the OPA683. Long PC board
traces, unmatched cables, and connections to multiple de-
vices can easily cause this value to be exceeded. Always
consider this effect carefully, and add the recommended
series resistor as close as possible to the OPA683 output pin
(see Board Layout Guidelines).
DISTORTION PERFORMANCE
The OPA683 provides low distortion in a very low power
amplifier. The CFB
plus
architecture also gives two significant
areas of distortion improvement. First, in operating regions
where the 2nd-harmonic distortion due to output stage
nonlinearities is very low (frequencies < 1MHz, low output
swings into light loads) the linearization at the inverting node
provided by the CFB
plus
design gives 2nd-harmonic distor-
tions that extend into the
–
90dBc region. Previous current
feedback amplifiers have been limited to approximately
–
85dBc due to the nonlinearities at the inverting input. The
second area of distortion improvement comes in a distortion
performance that is more gain independent than prior solu-
tions. To the extent that the distortion at a particular output
power is output stage dependent, 2nd-harmonic particularly,
and to a lesser extend 3rd-harmonic distortion, is constant as
the gain is increased. This is due to the constant loop gain
versus signal gain provided by the CFB
plus
design. As shown
in the Typical Characteristics, while the 2nd-harmonic is
constant with gain, the 3rd-harmonic degrades at higher
gains.
Relative to alternative amplifiers with < 1mA supply current,
the OPA683 holds much lower distortion at higher frequen-
cies (> 5MHz) and to higher gains. Generally, until the
fundamental signal reaches very high frequency or power
levels, the 2nd-harmonic will dominate the distortion with a
lower 3rd-harmonic component. Focusing then on the 2nd-
harmonic, increasing the load impedance improves distortion
slightly for the OPA683. Remember that the total load in-
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
OPA683IDBVRG4 功能描述:高速運(yùn)算放大器 Very Lo-Pwr Current Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
OPA683IDBVT 功能描述:高速運(yùn)算放大器 Very Lo-Pwr Current Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
OPA683IDBVTG4 功能描述:高速運(yùn)算放大器 Very Lo-Pwr Current Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
OPA683IDG4 功能描述:高速運(yùn)算放大器 Very Lo-Pwr Current Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
OPA683IDR 功能描述:高速運(yùn)算放大器 Very Lo-Pwr Current Feedback RoHS:否 制造商:Texas Instruments 通道數(shù)量:1 電壓增益 dB:116 dB 輸入補(bǔ)償電壓:0.5 mV 轉(zhuǎn)換速度:55 V/us 工作電源電壓:36 V 電源電流:7.5 mA 最大工作溫度:+ 85 C 安裝風(fēng)格:SMD/SMT 封裝 / 箱體:SOIC-8 封裝:Tube
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