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參數(shù)資料
| 型號： | OPA569 |
| 英文描述： | Power Op Amp. Output Signal Swings Within 200mV of Rails at 2A Output Current |
| 中文描述： | 功率運(yùn)算放大器。輸出信號擺幅在200mV的Rails的輸出電流為2A |
| 文件頁數(shù)： | 17/23頁 |
| 文件大?。?/td> | 411K |
| 代理商： | OPA569 |
OPA569
SBOS264
17
www.ti.com
Junction temperature should be kept below 125
°
C for reliable
operation. The junction temperature can be calculated by:
T
J
= T
A
+ P
D
θ
JA
where
θ
JA
=
θ
JC
+
θ
CA
T
J
= Junction Temperature (
°
C)
T
A
= Ambient Temperature (
°
C)
P
D
= Power Dissipated (W)
θ
JA
= Junction-to-Ambient Thermal Resistance
θ
JC
= Junction-to-Case Thermal Resistance
θ
CA
= Case-to-Air Thermal Resistance
The Maximum Power Dissipation vs Temperature for the
above heatsinking methods is shown in Figure 11.
To appropriately determine required heatsink area, required
power dissipation should be calculated and the relationship
between power dissipation and thermal resistance should be
considered to minimize shutdown conditions and allow for
proper long-term operation (junction temperature of 125
°
C).
Once the heatsink area has been selected, worst-case load
conditions should be tested to ensure proper thermal protec-
tion.
For applications with limited board size, refer to Figure 12 for
the approximate thermal resistance relative to heatsink area.
Increasing the heatsink area beyond 2in
2
provides little
improvement in thermal resistance. To achieve the 21.5
°
C/W
stated in the Electrical Characteristics, a copper plane size of
9in
2
was used. The SO-20 PowerPAD package is well suited
for continuous power levels, as shown in Figure 11. Higher
power levels may be achieved in applications with a low
on/off duty cycle.
FIGURE 11. Maximum Power Dissipation vs Temperature.
FEEDBACK CAPACITOR IMPROVES RESPONSE
For optimum settling time and stability with higher impedance
feedback networks (R
F
> 50k
), it may be necessary to add
a feedback capacitor across the feedback resistor, R
F
, as
shown in Figure 13. This capacitor compensates for the zero
created by the feedback network impedance and the OPA569
input capacitance (and any parasitic layout capacitance).
The effect becomes more significant with higher impedance
networks.
The size of the capacitor needed is estimated using the
equation:
R
IN
C
IN
= R
F
C
F
where C
IN
is the sum of the input capacitance of the OPA569
plus the parasitic layout capacitance.
14
12
10
8
6
4
2
0
Temperature (
°
C)
MAXIMUM POWER DISSIPATION
vs TEMPERATURE
P
–
55
–
30
20
–
5
45
70
95
120
Copper
—
Soldered
with 250lfm Airlow
Copper
—
Soldered
with 150lfm Airlow
Copper
—
Soldered
without Forced Air
No Copper
Copper
—
Unsoldered
Copper
—
Soldered
with 500lfm Airlow
FIGURE 12. Thermal Resistance vs Circuit Board Copper
Area.
35
30
25
20
15
10
T
θ
J
°
C
0
1
2
3
4
5
Copper Area (inches
2
)
THERMAL RESISTANCE vs COPPER AREA
OPA569
Surface-Mount Package
OPA569
V+
V
–
V
OUT
V
IN
R
IN
5
12,
13
14,
15
17,
18
6
R
IN
C
IN
= R
F
C
F
R
F
C
L
C
IN
C
IN
C
F
Where C
is equal to the OPA569
’
s input
capacitance (approximately 9pF) plus any
parasitic layout capacitance.
FIGURE 13. Feedback Capacitor for use with Higher Imped-
ance Networks.
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