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參數(shù)資料
| 型號： | NCV7361ADR2G |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | Buffer和線驅(qū)動 |
| 英文描述： | Voltage Regulator with Integrated LIN Transceiver; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500 |
| 中文描述： | LINE TRANSCEIVER, PDSO8 |
| 封裝： | SOIC-8 |
| 文件頁數(shù)： | 6/27頁 |
| 文件大?。?/td> | 272K |
| 代理商： | NCV7361ADR2G |
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NCV7361A
http://onsemi.com
14
Figure 18. Receive Mode Impulse Diagram
60%
t < tdeb_BUS
VSUP
RxD
40%
BUS
50%
Vthr_max
Vthr_min
Vthr_hys
Vthr_cnt
t < tdeb_BUS
The receive threshold values Vthr_max and Vthr_min are
symmetrical to 0.5*VSUP with a hysteresis of 0.135*VSUP.
The LIN specific receive threshold is between 0.4*VSUP
and 0.6 * VSUP.
Data Rate
The NCV7361A is a constant slew rate transceiver. The
bus driver works with a fixed slew rate range of 1.0 V/
ms
v DV/DT v 2.5 V/ms. This principle provides good
symmetry of the slope times between recessive to dominant
and dominant to recessive slopes within the LIN bus load
range (CBUS, Rterm).
The NCV7361A guarantees data rates up to 20 kb within
the complete bus load range under worst case conditions.
The constant slew rate principle holds appropriate voltage
levels and can operate within the LIN Protocol
Specification for RC oscillator systems with a matching
tolerance up to
"2% between 2 nodes.
TxD Input
The 5.0 V input TxD directly controls the BUS level:
TxD = low
→ BUS = low (dominant level)
TxD = high
→ BUS = high (recessive level)
The TxD pin has an internal pullup resistor connected to
VOUT. This guarantees that an open TxD pin generates a
recessive BUS level.
Figure 19. TxD Input Circuitry
RC Filter
(10 ns)
Typ.
15 k
NCV7361A
MCU
TxD
RPU_TxD
IPU_TxD
VCC
VOUT
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