參數(shù)資料
型號： NCV7361ADR2G
廠商： ON SEMICONDUCTOR
元件分類： Buffer和線驅(qū)動
英文描述： Voltage Regulator with Integrated LIN Transceiver; Package: SOIC-8 Narrow Body; No of Pins: 8; Container: Tape and Reel; Qty per Container: 2500
中文描述： LINE TRANSCEIVER, PDSO8
封裝： SOIC-8
文件頁數(shù)： 24/27頁
文件大?。?/td> 272K
代理商： NCV7361ADR2G
NCV7361A
http://onsemi.com
6
ELECTRICAL CHARACTERISTICS (7.0 V v VSUP v 18 V, 40°C v TA v 125°C unless otherwise noted)
Characteristic
Symbol
Condition
Min
Typ
Max
Unit
RESET AC CHARACTERISTICS
Reset Time
tRes
50
100
140
ms
Reset Rise Time (Note 9)
trr
3.0
7.5
15
ms
BUS Debounce Time (Note 14)
tdeb_BUS
1.5
2.8
4.0
ms
WakeUp Time
tWake_BUS
25
60
120
ms
GENERAL LIN BUS INTERFACE AC CHARACTERISTICS
Transmit Propagation Delay
TxD > BUS (Notes 10 and 11)
tdr_TxD,
tdf_TxD
RL/CL at BUS
1.0 kW/1.0 nF
660 W/6.8 nF
500 W/10 nF
VSUPMIN = 8 V
4.0
ms
Symmetry of Propagation Delay
BUS > RxD (Note 10)
tdsym_TxD
tdr_TxD tdf_TxD
VSUPMIN = 8 V
2.0
2.0
ms
Receiver Propagation Delay
BUS > RxD (Notes 10 and 11)
tdr_RxD
tdf_RxD
CL(RxD) = 50 pF
VSUPMIN = 8 V
6.0
ms
Symmetry of Propagation Delay
TxD > BUS (Note 10)
tdsym_RxD
tdr_RxD tdf_RxD
VSUPMIN = 8 V
2.0
2.0
ms
Slew Rate BUS Rising Edge (Note 9)
dV/dTrise
20% v VBUS v 80%
CL = 1.0 nF, RL = 1.0 kW
VSUPMIN = 8 V
1.0
1.7
2.5
V/ms
Slew Rate BUS Falling Edge (Note 9)
dV/dTfall
20% v VBUS v 80%
CL = 1.0 nF, RL = 1.0 kW
VSUPMIN = 8 V
2.5
1.7
1.0
V/ms
LIN BUS PARAMETER ACCORDING TO LIN SPEC. REV. 1.3
Slope Time, Transition from Recessive to
Dominant (Notes 11 and 12)
tsdom
VSUP = 8.0 V
RL = 500 W/CL = 10 nF
12
ms
Slope Time, Transition from Dominant to
Recessive (Notes 11 and 13)
tsrec
VSUP = 8.0 V
RL = 500 W/CL = 10 nF
12
ms
Slope Time Symmetry
tssym
VSUP = 8.0 V
RL = 500 W/CL = 10 nF
Tssym = tsdom tsrec
7.0
1.0
ms
Slope Time, Transition from Recessive to
Dominant (Notes 11 and 12)
tsdom
VSUP = 18 V
RL = 500 W/CL = 10 nF
18
ms
Slope Time, Transition from Dominant to
Recessive (Notes 11 and 13)
tsrec
VSUP = 18 V
RL = 500 W/CL = 10 nF
18
ms
Slope Time Symmetry
tssym
VSUP = 18 V
RL = 500 W/CL = 10 nF
Tssym = tsdom tsrec
5.0
5.0
ms
9. Not production tested, guaranteed by design and qualification.
10.See Figures 2 and 3, Timing Diagrams.
11. See Figures 5, 6, 7, 8, and 9 for test setup.
12.tsdom = (tVBUS40% tVBUS95%) / 0.55.
13.tsdom = (tVBUS60% tVBUS5%) / 0.55.
14.See Figure 18.
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