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參數(shù)資料
| 型號： | NCP1094MNRG |
| 廠商： | ON Semiconductor |
| 文件頁數(shù)： | 7/12頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC INTERFACE CTLR POE-PD 10-DFN |
| 標準包裝： | 1 |
| 系列： | HIPO™ |
| 控制器類型： | PoE-PD 接口 |
| 接口： | IEEE 802.3af |
| 電流 - 電源： | 500mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 10-VFDFN 裸露焊盤 |
| 供應(yīng)商設(shè)備封裝： | 10-DFN-EP（3x3） |
| 包裝： | 標準包裝 |
| 其它名稱： | NCP1094MNRGOSDKR |
NCP1093, NCP1094
http://onsemi.com
4
Table 1. PIN DESCRIPTION
Name
Pin No.
Type
Description
NCP1093
NCP1094
INRUSH
1
Output
Current limit programming pin. Connect a resistor between INRUSH and
VPORTN.
CLASS
2
Output
Classification current programming pin. Connect a resistor between CLASS
and VPORTN.
DET
3
Output,
Open Drain
Detection pin. Connect a 24.9 kW resistor between DET and VPORTP for a
valid PD detection signature.
VPORTN1
4
Ground
Negative input power. Connected to the source of the internal passswitch
VPORTN2
5
Ground
Negative input power. Connected to the source of the internal passswitch
RTN
6
Ground
DCDC controller power return. Connected to the drain of the internal pass
switch
PGOOD
7
Output,
Open Drain
Open Drain Power Good Indicator. Pin is in HZ mode when the power good
signal is active.
UVLO
8
Input
Undervoltage lockout input. Voltage with respect to VPORTN. Connect a resist-
ordivider from VPORTP to UVLO to VPORTNx to set an external UVLO
threshold.
AUX
8
Input
Auxiliary Pin. When this pin is pulled up, the Pass Switch is disabled and allows
a supply transition from PSE to the rear auxiliary supply connected between
VPORTP and RTN.
NCLASS_AT
9
Output
Active low enable signal used to verify high power operation
VPORTP
10
Input
Positive input power. Voltage with respect to VPORTN.
Exposed Pad
EP
Ground
Exposed pad should be connected to VPORTN.
Table 2. ABSOLUTE MAXIMUM RATINGS
Symbol
Parameter
Min
Max
Units
Conditions
VPORTP
Input power supply
0.3
72
V
Voltage with respect to VPORTN
RTN
Analog ground supply 2
0.3
72
V
Passswitch in offstate (voltage with respect to VPORTN)
CLASS
Analog output
0.3
72
V
Voltage with respect to VPORTN
INRUSH
Analog output
0.3
3.6
V
Voltage with respect to VPORTN
AUX
Analog input
0.3
72
V
Voltage with respect to VPORTN
UVLO
Analog input
0.3
3.6
V
Voltage with respect to VPORTN
PGOOD
Analog output
0.3
72
V
Voltage with respect to RTN
TA
Ambient temperature
40
85
°C
TJ
Junction temperature
125
°C
TJ, TSD
Junction temperature
(Note 1)
175
°C
Thermal shutdown condition
TSTG
Storage Temperature
55
150
°C
TqJA
Thermal Resistance,
Junction to Air (Note 2)
50
°C/W
DFN10
ESDHBM
Human Body Model
2
kV
per EIAJESD22A114 standard
ESDCDM
Charged Device Model
500
V
per ESDSTM5.3.1 standard
ESDMM
Machine Model
200
V
per EIAJESD22A115A standard
LU
Latchup
±100
mA
per JEDEC Standard JESD78
Stresses exceeding Maximum Ratings may damage the device. Maximum Ratings are stress ratings only. Functional operation above the
Recommended Operating Conditions is not implied. Extended exposure to stresses above the Recommended Operating Conditions may affect
device reliability.
1. TjTSD allowed during error conditions only. It is assumed that this maximum temperature condition does not occur more than 1 hour
cumulative during the useful life for reliability reasons.
2. Low qJA is obtained with 2S2P test board (2 signal 2 plane). High qJA is obtained with double sideboard with minimum pad area and natural
convection. Refer to Jedec JESD51 for details. The exposed pad must be connected to the VPORTN ground pin.
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