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參數(shù)資料
| 型號： | NB4N441 |
| 廠商： | ON SEMICONDUCTOR |
| 英文描述： | 3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Differential LVPECL Output(3.3V串行輸入多協(xié)議PLL時鐘合成器, 差分LVPECL輸出) |
| 中文描述： | 3.3串行輸入多協(xié)議PLL時鐘合成器，差分LVPECL輸出電壓（3.3V串行輸入多協(xié)議PLL的時鐘合成器，差分LVPECL的輸出） |
| 文件頁數(shù)： | 8/12頁 |
| 文件大小： | 168K |
| 代理商： | NB4N441 |
NB4N441
http://onsemi.com
8
Figure 4. Power Supply Filter
PLL_V
CC
V
CC
0.01 F
47 F
L=1000 H
R=15
0.01 F
3.3 V or
5.0 V
R
S
= 5
3.3 V or
5.0 V
Power Supply Filtering
The NB4N441 is a mixed analog/digital product and as
such, it exhibits some sensitivities that would not necessarily
be seen on a fully digital product. Analog circuitry is
naturally susceptible to random noise, especially if this noise
is seen on the power supply pins. The NB4N441 provides
separate power supplies for the digital circuitry (V
CC
) and
the internal PLL (PLL_V
CC
) of the device. The purpose of
this design technique is to try and isolate the high switching
noise of the digital outputs from the relatively sensitive
internal analog phase
locked loop. In a controlled
environment such as an evaluation board, this level of
isolation is sufficient. However, in a digital system
environment where it is more difficult to minimize noise on
the power supplies, a second level of isolation may be
required. The simplest form of isolation is a power supply
filter on the PLL_V
CC
Pin for the NB4N441. Figure 4
illustrates a typical power supply filter scheme. The
NB4N441 is most susceptible to noise with spectral content
in the 1 kHz to 1 MHz range. Therefore, the filter should be
designed to target this range. The key parameter that needs
to be met in the final filter design is the DC voltage drop that
will be seen between the V
CC
supply and the PLL_V
CC
pin
of the NB4N441. From the data sheet, the PLL_V
CC
current
(the current sourced through the PLL_V
CC
Pin) is typically
26 mA. Assuming that a minimum of 2.9 V must be
maintained on the PLL_V
CC
pin, very little DC voltage drop
can be tolerated when a 3.3 V V
CC
supply is used. The
resistor shown in Figure 4 must have a resistance of 5
Max to meet the voltage drop criteria. The RC filter pictured
will provide a broadband filter with approximately 100:1
attenuation for noise whose spectral content is above
20 kHz. As the noise frequency crosses the series resonant
point of an individual capacitor, it’s overall impedance
begins to look inductive and thus increases with increasing
frequency. The parallel capacitor combination shown
ensures that a low impedance path to ground exists for
frequencies well above the bandwidth of the PLL. The level
of required filtering is subject to further optimization and
simplification. All the V
CC
pins are connected to the same
V
CC
plane. All the ground pins (GND) are connected to the
same GND plane.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| NB4N441_07 | 制造商:ONSEMI 制造商全稱:ON Semiconductor 功能描述:3.3V Serial Input MultiProtocol PLL Clock Synthesizer, Differential LVPECL Output |
| NB4N441MNG | 功能描述:鎖相環(huán) - PLL MLTPRTCL PLL CLK SYN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NB4N441MNGEVB | 功能描述:BOARD EVAL NB4N441MNG RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:* 產(chǎn)品培訓模塊:Obsolescence Mitigation Program 標準包裝:1 系列:- 主要目的:電源管理，電池充電器 嵌入式:否 已用 IC / 零件:MAX8903A 主要屬性:1 芯鋰離子電池 次要屬性:狀態(tài) LED 已供物品:板 |
| NB4N441MNR2G | 功能描述:鎖相環(huán) - PLL MLTPRTCL PLL CLK SYN RoHS:否 制造商:Silicon Labs 類型:PLL Clock Multiplier 電路數(shù)量:1 最大輸入頻率:710 MHz 最小輸入頻率:0.002 MHz 輸出頻率范圍:0.002 MHz to 808 MHz 電源電壓-最大:3.63 V 電源電壓-最小:1.71 V 最大工作溫度:+ 85 C 最小工作溫度:- 40 C 封裝 / 箱體:QFN-36 封裝:Tray |
| NB4N507A | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:3.3V/5V, 50 MHz to 200 MHz PECL Clock Synthesizer |
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