參數(shù)資料
型號(hào)： NAND512R4A2CZD6E
廠(chǎng)商： NUMONYX
元件分類(lèi)： PROM
英文描述： 32M X 16 FLASH 1.8V PROM, 15000 ns, PBGA55
封裝： 8 X 10 MM, 1 MM HEIGHT, ROHS COMPLIANT, VFBGA-55
文件頁(yè)數(shù)： 16/55頁(yè)
文件大小： 1377K
代理商： NAND512R4A2CZD6E
NAND512-A2C
Device operations
6.2.2
Page read
After the random read access the page data is transferred to the page buffer in a time of
tWHBH (refer to Table 21 for value). Once the transfer is complete the Ready/Busy signal
goes High. The data can then be read out sequentially (from selected column address to
last column address) by pulsing the Read Enable signal.
Figure 9.
Read (A,B,C) operations
6.2.3
Sequential row read
After the data in last column of the page is output, if the Read Enable signal is pulsed and
Chip Enable remains Low, then the next page is automatically loaded into the page buffer
and the read operation continues. A sequential row read operation can only be used to read
within a block. If the block changes a new read command must be issued. Refer to
diagrams for details about sequential row read operations. To terminate a sequential row
read operation, set to High the Chip Enable signal for more than tEHEL. Sequential row read
is not available when the Chip Enable don’t care option is enabled.
CL
E
W
AL
R
I/O
RB
00h/
01h/ 50h
ai07595c
Busy
Command
code
Address input
Data output (sequentially)
tBLBH1
(read)
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