參數(shù)資料
型號(hào): NAND128R3A2BV1E
廠商: 意法半導(dǎo)體
英文描述: 128 Mbit, 256 Mbit, 512 Mbit, 1 Gbit (x8/x16) 528 Byte/264 Word Page, 1.8V/3V, NAND Flash Memories
中文描述: 128兆,256兆,512兆位,1千兆位(x8/x16)528 Byte/264字的頁(yè)面,1.8V/3V,NAND閃存芯片
文件頁(yè)數(shù): 38/57頁(yè)
文件大小: 410K
代理商: NAND128R3A2BV1E
NAND128-A, NAND256-A, NAND512-A, NAND01G-A
38/57
Table 21. AC Characteristics for Operations
Alt.
Symbol
Note: 1. The time to Ready depends on the value of the pull-up resistor tied to the Ready/Busy pin. See Figures
34
,
35
and
36
.
2. To break the sequential read cycle, E must be held High for longer than t
EHEL
.
3. ES = Electronic Signature.
Symbol
Parameter
1.8V
Devices
3V
Devices
Unit
t
ALLRL1
t
AR
Address Latch Low to
Read Enable Low
Read Electronic Signature
Min
10
10
ns
t
ALLRL2
Read cycle
Min
10
10
ns
t
BHRL
t
RR
Ready/Busy High to Read Enable Low
Min
20
20
ns
t
BLBH1
Ready/Busy Low to
Ready/Busy High
Read Busy time, 128Mb, 256Mb,
512Mb Dual Die
Max
12
12
μs
Read Busy time, 512Mb, 1Gb
Max
15
12
μs
t
BLBH2
t
PROG
Program Busy time
Max
500
500
μs
t
BLBH3
t
BERS
Erase Busy time
Max
3
3
ms
t
BLBH4
Reset Busy time, during ready
Max
5
5
μs
t
WHBH1
t
RST
Write Enable High to
Ready/Busy High
Reset Busy time, during read
Max
5
5
μs
Reset Busy time, during program
Max
10
10
μs
Reset Busy time, during erase
Max
500
500
μs
t
CLLRL
t
CLR
Command Latch Low to Read Enable Low
Min
10
10
ns
t
DZRL
t
IR
Data Hi-Z to Read Enable Low
Min
0
0
ns
t
EHBH
t
CRY
Chip Enable High to Ready/Busy High (E intercepted read)
Max
60 + t
r(1)
60 + t
r(1)
ns
t
EHEL
t
CEH
Chip Enable High to Chip Enable Low
(2)
Min
100
100
ns
t
EHQZ
t
CHZ
Chip Enable High to Output Hi-Z
Max
20
20
ns
t
ELQV
t
CEA
Chip Enable Low to Output Valid
Max
45
45
ns
t
RHBL
t
RB
Read Enable High to Ready/Busy Low
Max
100
100
ns
t
RHRL
t
REH
Read Enable High to
Read Enable Low
Read Enable High Hold time
Min
15
15
ns
t
RHQZ
t
RHZ
Read Enable High to Output Hi-Z
Min
15
15
ns
Max
30
30
t
RLRH
t
RP
Read Enable Low to
Read Enable High
Read Enable Pulse Width
Min
30
30
ns
t
RLRL
t
RC
Read Enable Low to
Read Enable Low
Read Cycle time
Min
60
50
ns
t
RLQV
t
REA
Read Enable Low to
Output Valid
Read Enable Access time
Max
35
35
ns
Read ES Access time
(3)
t
WHBH
t
R
Write Enable High to
Ready/Busy High
Read Busy time, 128Mb, 256Mb,
512Mb Dual Die
Max
12
12
μs
Read Busy time, 512Mb, 1Gb
Max
15
12
μs
t
WHBL
t
WB
Write Enable High to Ready/Busy Low
Max
100
100
ns
t
WHRL
t
WHR
Write Enable High to Read Enable Low
Min
80
60
ns
t
WLWL
t
WC
Write Enable Low to
Write Enable Low
Write Cycle time
Min
60
50
ns
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