參數(shù)資料
型號(hào): MVTX2803AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Unmanaged 8-Port 1000 Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA596
封裝: 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
文件頁數(shù): 18/127頁
文件大小: 1706K
代理商: MVTX2803AG
MVTX2803
Data Sheet
18
Zarlink Semiconductor Inc.
5.3.3 Aging
Aging time is controlled by register 400h and 401h.
The aging module scans and ages MCT entries based on a programmable "age out" time interval. As indicated
earlier, the search module updates the source MAC address and VLAN port association timestamps for each
frame it processes. When an entry is ready to be aged, the entry is removed from the table.
5.3.4 Data Structure
The MCT data structure is used when searching for MAC addresses. The structure is maintained by hardware
in the search engine. The database is essentially a hash table, with collisions resolved by chaining. The
database is partial external, and partial internal, as described earlier: the first MCT entry of each linked list is
always located in the external SRAM, and the subsequent MCT’s are located internally.
6.0 Frame Engine
6.1 Data Forwarding Summary
Data enters the device at the RxMAC, the RxDMA will move the data from the MAC RxFIFO to the FDB. Data is
moved in 8-byte granules in conjunction with the scheme for the SRAM interface.
A switch request is sent to the Search Engine. The Search Engine processes the switch request.
A switch response is sent back to the Frame Engine and indicates whether the frame is unicast or multicast,
and its destination port or ports.
A Transmission Scheduling Request is sent in the form of a signal notifying the TxQ manager. Upon
receiving a Transmission Scheduling Request, the device will format an entry in the appropriate
Transmission Scheduling Queue (TxSch Q) or Queues. There are 8 TxSch Queues for each Gigabit port,
one for each priority. Creation of a queue entry either involves linking a new job to the appropriate linked
list if unicast, or adding an entry to a physical queue if multicast.
When the port is ready to accept the next frame, the TxQ manager will get the head-of-line (HOL) entry of
one of the TxSch Qs, according to the transmission scheduling algorithm (so as to ensure per-class quality
of service). The unicast linked list and the multicast queue for the same port-class pair are treated as one
logical queue.
The TxDMA will pull frame data from the memory and forward it granule-by-granule to the MAC TxFIFO of
the destination port.
6.2 Frame Engine Details
This section briefly describes the functions of each of the modules of the MVTX2803AG frame engine.
6.2.1 FCB Manager
The FCB manager allocates FCB handles to incoming frames, and releases FCB handles upon frame
departure. The FCB manager is also responsible for enforcing buffer reservations and limits. The default values
can be determined by referring to Chapter 8. In addition, the FCB manager is responsible for buffer aging, and
for linking unicast forwarding jobs to their correct TxSch Q. The buffer aging can be enabled or disabled by the
bootstrap pin and the aging time is defined in register FCBAT.
6.2.2 Rx Interface
The Rx interface is mainly responsible for communicating with the RxMAC. It keeps track of the start and end of
frame and frame status (good or bad). Upon receiving an end of frame that is good, the Rx interface makes a
switch request.
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