
MVTX2803
Data Sheet
14
Zarlink Semiconductor Inc.
2.1.6 Stop Condition
Generated by the master, the MVTX2803AG. The bus is considered to be free after the Stop condition is
generated. The Stop condition occurs if while the SCL line is High, there is a Low-to-High transition of the SDA.
The I
2
C interface serves the function of configuring the MVTX2803AG at boot time. The master is the
MVTX2803AG, and the slave is the EEPROM memory.
2.2 Synchronous Serial Interface
The synchronous serial interface serves the function of configuring the MVTX2803AG
not
at boot time but via a
PC. The PC serves as master and the MVTX2803AG serves as slave. The protocol for the synchronous serial
interface is nearly identical to the I
2
C protocol. The main difference is that there is no acknowledgment bit after
each byte of data transferred.
The unmanaged MVTX2803AG uses a synchronous serial interface to program the internal registers. To
reduce the number of signals required, the register address, command and data are shifted in serially through
the PS_DI pin. PS_STROBE pin is used as the shift clock. PS_DO pin is used as data return path.
Each command consists of four parts.
Any command can be aborted in the middle by sending an ABORT pulse to the MVTX2803AG.
START pulse
Register Address
Read or Write command
Data to be written or read back
A START command is detected when PS_DI is sampled high at PS_STROBE - leading edge, and PS_DI is sampled
low when STROBE- falls.
An ABORT command is detected when PS_DI is sampled low at PS_STROBE - leading edge, and PS_DI is sampled
high when PS_STROBE - falls.
2.2.1 Write Command
2.2.2 Read Command
All registers in the MVTX2803AG can be modified through this synchronous serial interface.
PS-STROBE-
PS_DI
START
ADDRESS
COMMAND
DATA
W
A0
A1
A2
...
A9 A10 A11
D0
D1
D2 D3
D4 D5
D6
D7
2 extra clocks after
last transfer
PS-STROBE-
PS_DI
START
ADDRESS
COMMAND
DATA
R
A0
A1
A2
...
A9 A10 A11
PS_DO
D0
D1
D2
D3
D4
D5
D6
D7