參數(shù)資料
型號: MVTX2802AG
廠商: ZARLINK SEMICONDUCTOR INC
元件分類: 網(wǎng)絡(luò)接口
英文描述: Managed 4-Port 1000 Mbps Ethernet Switch
中文描述: DATACOM, LAN SWITCHING CIRCUIT, PBGA596
封裝: 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596
文件頁數(shù): 71/154頁
文件大?。?/td> 1936K
代理商: MVTX2802AG
MVTX2802
Data Sheet
71
Zarlink Semiconductor Inc.
Bit [4]: Port 1 statistic counter Wrap around interrupt mask.
(Default 1’b1)
Bit [5]: Port 1 Link change mask.
(Default 1’b1)
11.7.1.11 INTP_MASK1 – Interrupt Mask for MAC Port 2,3
CPU Address:h30D
Accessed by CPU, serial interface (R/W)
11.7.2 RQS – Receive Queue Select
CPU Address:h310
Accessed by CPU, serial interface (RW)
This register selects which receive queue is enable to send data to the CPU.
Bit[0]: Select Queue 0. If set to one, this queue may be scheduled to CPU port. If set to zero, this queue will be
blocked. If multiple queues are selected, a strict priority will be applied. Q3> Q2> Q1> Q0. Same applies to bits
[3:1]. See QoS application note for more information.
Bit[1]: Select Queue 1
Bit[2]: Select Queue 2
Bit[3]: Select Queue 3
Note
:
Strip priority applies between different selected queues (Q3>Q2>Q1>Q0)
Bit[4]: Enable flush Queue 0
Bit[5]: Enable flush Queue 1
Bit[6]: Enable flush Queue 2
Bit[7]: Enable flush Queue 3
When flush (drop frames) is enable, it starts when queue is too long or entry is too old. A queue is too long
when it reaches WRED thresholds. Queue 0 is not subject to early drop. Packets in queue 0 are dropped only
when the queue is too old. An entry is too old when it is older than the time programmed in the register TX_AGE
[5:0]. CPU can dynamically program this register reading register RQSS [7:4].
7
6
5
4
3
2
1
0
P3
P2
Bit [0]:
Port 2 WAS mask (Default 1’b1)
Bit [1]:
Port 2 link change mask (Default 1’b1)
Bit [4]:
Port 3 WAS mask (Default 1’b1)
Bit [5]:
Port 3 link change mask (Default 1’b1)
7
4
3
0
FQ3
FQ2
FQ1
FQ0
SQ3
SQ2
SQ1
SQ0
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參數(shù)描述
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