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參數(shù)資料
| 型號(hào)： | MVTX2802AG |
| 廠商： | ZARLINK SEMICONDUCTOR INC |
| 元件分類(lèi)： | 網(wǎng)絡(luò)接口 |
| 英文描述： | Managed 4-Port 1000 Mbps Ethernet Switch |
| 中文描述： | DATACOM, LAN SWITCHING CIRCUIT, PBGA596 |
| 封裝： | 40 X 40 MM, 2.33 MM HEIGHT, MS-034, HSBGA-596 |
| 文件頁(yè)數(shù)： | 49/154頁(yè) |
| 文件大?。?/td> | 1936K |
| 代理商： | MVTX2802AG |
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MVTX2802
Data Sheet
49
Zarlink Semiconductor Inc.
11.2 Directly Accessed Registers
11.2.1 INDEX_REG0
Address bits [7:0] for indirectly accessed register addresses
Address = 0 (write only)
11.2.2 INDEX_REG1 (only needed for CPU 8-bit bus mode)
Address bits [15:8] for indirectly accessed register addresses
Address = 1 (write only)
11.2.3 DATA_FRAME_REG
Data of indirectly accessed registers. (8 bits)
Address = 2 (read/write)
11.2.4 CONTROL_FRAME_REG
CPU transmit/receive switch frames. (8/16 bits)
Address = 3 (read/write)
Format: (see processor interface application note for more information)
-
Send frame from CPU: (In sequence)
Frame Data (size should be in multiple of 8-byte)
8-byte of Frame status (Frame size, Destination port #, Frame O.K. status)
-
CPU Received frame: (In sequence)
8-byte of Frame status (Frame size, Source port #, VLAN tag)
Frame Data
11.2.5 COMMAND&STATUS
CPU interface commands (write) and status
Address = 4 (read/write)
When the CPU
reads
this register:
Bit [0]: Transmit Control Command 1 Ready; Must read true before CPU writes new Control Command 1.
Bit [1]: Receive Control Command 1 Ready; Must read true before CPU reads a new Control Command 1.
Bit [2]: Receive Control Command 2 Ready; Must read true before CPU reads a new Control Command 2.
Bit [3]: Receive CPU Frame Ready; Must read true before receiving a CPU frame and at every 8-byte boundary within
a CPU frame.
Bit [4]: Transmit CPU Frame Ready; Must read true before transmitting a CPU frame and at every 16-byte boundary
within a CPU frame.
Bit [5]: End of Receive CPU Frame to indicate that the last 8 bytes need to be read.
Bit [15:6]: Reserved.
When the CPU
writes
to this register:
Bit [0]: End of Transmit Control Command indicator; Set after CPU writes a Control Command Frame into Rx buffer.
Bit [1]: End of Receive Control Command 1 indicator; Set after CPU reads out a Control Command 1 Frame from Tx
buffer 1.
Bit [2]: End of Receive Control Command 2 indicator; Set after CPU reads out a Control Command 2 Frame from Tx
buffer 2.
Bit [3]: End of Receive CPU Frame indicator. Set after CPU reads out a CPU frame or to flush out the rest of CPU
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MVTX2803 | Unmanaged 8-Port 1000 Mbps Ethernet Switch |
| MVTX2803AG | Unmanaged 8-Port 1000 Mbps Ethernet Switch |
| MVTX2804 | 8-Port 1000 Mbps Ethernet Distributed Switch |
| MVTX2804AG | 8-Port 1000 Mbps Ethernet Distributed Switch |
| MVV200 | Analog IC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MVTX2803 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Unmanaged 8-Port 1000 Mbps Ethernet Switch |
| MVTX2803A | 制造商:未知廠家 制造商全稱(chēng):未知廠家 功能描述:Unmanaged 8 port Gigabit Ethernet switch |
| MVTX2803AG | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:Unmanaged 8-Port 1000 Mbps Ethernet Switch |
| MVTX2803AG2 | 制造商:Microsemi Corporation 功能描述: |
| MVTX2804 | 制造商:ZARLINK 制造商全稱(chēng):Zarlink Semiconductor Inc 功能描述:8-Port 1000 Mbps Ethernet Distributed Switch |
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