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參數(shù)資料
| 型號(hào)： | MTB15N06V |
| 廠商： | ON SEMICONDUCTOR |
| 元件分類： | JFETs |
| 英文描述： | 15 A, 60 V, 0.12 ohm, N-CHANNEL, Si, POWER, MOSFET |
| 封裝： | CASE 418B-02, D2PAK-3 |
| 文件頁(yè)數(shù)： | 4/11頁(yè) |
| 文件大小： | 274K |
| 代理商： | MTB15N06V |
MTB15N06V
http://onsemi.com
2
MAXIMUM RATINGS (TC = 25°C unless otherwise noted)
Rating
Symbol
Value
Unit
DrainSource Voltage
VDSS
60
Vdc
DrainGate Voltage (RGS = 1.0 MΩ)
VDGR
60
Vdc
GateSource Voltage — Continuous
GateSource Voltage — NonRepetitive (tp ≤ 10 ms)
VGS
VGSM
± 20
± 25
Vdc
Vpk
Drain Current — Continuous @ 25°C
Drain Current — Continuous @ 100°C
Drain Current — Single Pulse (tp ≤ 10 μs)
ID
IDM
15
8.7
45
Adc
Apk
Total Power Dissipation @ 25°C
Derate above 25°C
Total Power Dissipation @ TA = 25°C (1)
PD
55
0.37
3.0
Watts
W/°C
Watts
Operating and Storage Temperature Range
TJ, Tstg
55 to 175
°C
Single Pulse DraintoSource Avalanche Energy — Starting TJ = 25°C
(VDD = 25 Vdc, VGS = 10 Vdc, IL = 15 Apk, L = 1.0 mH, RG = 25 Ω)
EAS
113
mJ
Thermal Resistance — Junction to Case
Thermal Resistance — Junction to Ambient
Thermal Resistance — Junction to Ambient (1)
RθJC
RθJA
2.73
62.5
50
°C/W
Maximum Lead Temperature for Soldering Purposes, 1/8″ from case for 10 seconds
TL
260
°C
(1) When surface mounted to an FR4 board using the minimum recommended pad size.
Designer’s Data for “Worst Case” Conditions — The Designer’s Data Sheet permits the design of most circuits entirely from the information presented. SOA Limit
curves — representing boundaries on device characteristics — are given to facilitate “worst case” design.
Designer’s is a trademark of Motorola, Inc. TMOS is a registered trademark of Motorola, Inc.
Thermal Clad is a trademark of the Bergquist Company.
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