- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄359677 > MT90883IG (Zarlink Semiconductor Inc.) TDM to Packet Processors PDF資料下載
參數(shù)資料
| 型號： | MT90883IG |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁數(shù)： | 77/97頁 |
| 文件大?。?/td> | 702K |
| 代理商： | MT90883IG |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁第33頁第34頁第35頁第36頁第37頁第38頁第39頁第40頁第41頁第42頁第43頁第44頁第45頁第46頁第47頁第48頁第49頁第50頁第51頁第52頁第53頁第54頁第55頁第56頁第57頁第58頁第59頁第60頁第61頁第62頁第63頁第64頁第65頁第66頁第67頁第68頁第69頁第70頁第71頁第72頁第73頁第74頁第75頁第76頁當(dāng)前第77頁第78頁第79頁第80頁第81頁第82頁第83頁第84頁第85頁第86頁第87頁第88頁第89頁第90頁第91頁第92頁第93頁第94頁第95頁第96頁第97頁
MT90880/1/2/3
Data Sheet
77
Zarlink Semiconductor Inc.
Two factors affect the frequency stability while in Holdover. The first factor is the drift on the master clock
(S_CLK) frequency. Any drift in master clock frequency translates directly into drift on the holdover frequency.
Note that the absolute master clock accuracy does not affect the stability of the held frequency, only changes in
the master clock frequency while in holdover mode. For example, a 32 ppm master clock may have a
temperature coefficient of 0.1 ppm/
0
C. So, a 10
0
C change in temperature may result in an additional frequency
offset of 1 ppm, over and above the intrinsic accuracy of 0.06 ppm.
The second factor affecting stability is any large frequency jitter on the reference input prior to the reference
failure. This could cause the measured frequency to be inaccurate, resulting in an incorrect holdover frequency.
Jitter Transfer
In master mode, jitter on the incoming reference is attenuated by both a Phase Slope Limiter and the internal
Loop Filter. The Phase Slope Limiter limits the output phase slope to 7 ns per 125
μ
s. Therefore, even if the
phase slope of the input signal exceeds this rate, such as for low frequency input jitter with a very large
amplitude, the maximum output phase slope will be limited to 7 ns per 125
μ
s. The internal loop filter is a single
pole low-pass filter with a cutoff frequency of 1.25 Hz. This progressively attenuates all jitter above the cutoff
frequency at a rate of 20 dB/decade.
Figure 36 shows the DPLL jitter transfer function diagram across a wide range of frequencies, while Figure 37 is
the portion of the diagram from Figure 36 around 0dB of the jitter transfer amplitude. From this diagram it is
possible to see that the DPLL is a second order, type 2 PLL.
Figure 36 - DPLL Jitter Transfer Function Diagram Across a Wide Range of Frequencies
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT9088IG | TDM to Packet Processors |
| MT8960 | Integrated PCM Filter Codec |
| MT8963AE1 | Integrated PCM Filter Codec |
| MAQ2901CL | Circular Connector; No. of Contacts:85; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:40; Circular Contact Gender:Socket; Circular Shell Style:Wall Mount Receptacle RoHS Compliant: No |
| MAQ2901CS | Circular Connector; No. of Contacts:1; Series:; Body Material:Aluminum Alloy; Connecting Termination:Solder; Connector Shell Size:10S; Circular Contact Gender:Pin; Circular Shell Style:Wall Mount Receptacle; Insert Arrangement:10S-2 RoHS Compliant: No |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT9088IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9092 | 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:ISO2-CMOS ST-BUS⑩ FAMILY Digital Telephone with HDLC (HPhone-II) |
| MT9092AP | 制造商:Microsemi Corporation 功能描述: |
| MT9092AP1 | 制造商:Zarlink Semiconductor Inc 功能描述:DGTL TEL 44PLCC - Rail/Tube 制造商:Zarlink Semiconductor Inc 功能描述:PB FREE H-PHONE-PLUS PLCC |
| MT9092APR | 制造商:Microsemi Corporation 功能描述:DGTL TEL 44PLCC - Tape and Reel |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。