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參數(shù)資料
| 型號(hào)： | MT90883 |
| 廠商： | Zarlink Semiconductor Inc. |
| 英文描述： | TDM to Packet Processors |
| 中文描述： | TDM到分組處理器 |
| 文件頁(yè)數(shù)： | 67/97頁(yè) |
| 文件大?。?/td> | 702K |
| 代理商： | MT90883 |
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MT90880/1/2/3
Data Sheet
67
Zarlink Semiconductor Inc.
Figure 29 - Connecting the MT90880 to Multiple External Memory Devices
6.9.4 External Memory Interface Timing
The timings for the external memory interface are shown in Table 39. However, calculations to see whether the
MT90880 will be capable of operation with a particular memory device also depend on some external factors,
notably the skew on the board between the system clock S_CLK at the MT90880 and the memory device.
For example, the diagram in Figure 52 shows the memory write cycle. The MT90880 puts out the data on the
bus at time T
RDV
following the rising edge of S_CLK. This has to meet a setup time to the next rising edge of
S_CLK at the RAM (T
DS
). However, if the clock is skewed on the board such that S_CLK is slightly earlier at the
RAM than at the MT90880, the setup time is effectively increased by the amount of skew.
The maximum clock skew between devices can be determined from the following equation:
Maximum allowable clock skew
For a Micron MT58L256L32P, the minimum RAM data setup time T
DS
is 1.5 ns when using the 7.5 ns speed
grade part. T
RDV
is 10 ns (from Table 41) and with S_CLK running at 66 MHz, the clock period T
S_CLK
is 15.15
ns. Therefore,
= T
S_CLK
- T
RDV
- T
DS
Micron
TM
generic SRAM
e.g. MT58L256L32P
(256K x 3e.g. MT58L256L32P
TM
)
(256K x 3e.g. MT58L256L32P
TM
)
(256K x Ae.g. MT58L256L32P
TM
)
(25GW#
TM
)
CLK
SA0
SA1
SA
ADSC#
DQd
DQc
DQb
DQa
ADV#
MODE
ADSC#
CE2
ZZ
CE2#
BWa#
CE#
BWc#
BWd#
BWb#
OE#
GW#
TM
TM
CLK
SA0
SA1
SA
ADSC#
DQd
DQc
DQb
DQa
ADV#
MODE
CE2
GW#
ADSP#
ZZ
CE2#
BWa#
CE#
BWc#
BWd#
BWb#
OE#
GW#
CLK
SA0
SA1
SA
ADSC#
DQd
DQc
DQb
DQa
ADV#
MODE
CE2
GW#
ADSP#
ZZ
CE2#
BWa#
CE#
BWc#
BWd#
BWb#
OE#
GW#
CLK
SA0
SA1
SA
DQd
DQc
DQb
DQa
ADV#
MODE
CE2
BWE#
ADSP#
ZZ
CE2#
BWa#
CE#
BWc#
BWd#
BWb#
OE#
GW#
66 MHz
System Clock
MT9088x device
RAM_A[19:4]
RAM_D[31:24]
RAM_ADSC#
S_CLK
RAM_A[2]
RAM_A[3]
RAM_D[7:0]
RAM_D[15:8]
RAM_D[23:16]
RAM_OE[3]#
RAM_OE[0]#
RAM_OE[1]#
RAM_OE[2]#
RAM_WE[3]#
RAM_WE[0]#
RAM_WE[1]#
RAM_WE[2]#
V
DD
V
SS
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| MT91600 | Programmable SLIC |
| MT91600AN | Programmable SLIC |
| MT91600AN1 | Programmable SLIC |
| MT91600ANR | Programmable SLIC |
| MT91600ANR1 | Programmable SLIC |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| MT90883A | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883A/IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883BP1N | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT90883IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
| MT9088IG | 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:TDM to Packet Processors |
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