參數(shù)資料
型號(hào)： MT9074
廠商： Mitel Networks Corporation
英文描述： T1/E1/J1 Single Chip Transceiver(T1/E1/J1單片收發(fā)器)
中文描述： T1/E1/J1收發(fā)單芯片收發(fā)器（T1/E1/J1收發(fā)單片收發(fā)器）
文件頁(yè)數(shù)： 59/120頁(yè)
文件大?。?/td> 362K
代理商： MT9074
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Advance Information
MT9074
59
Bit
Name
Functional Description
7 - 0 PS7-0 This counter is incremented for each
PRBS error detected on any of the
receive channels connected to the
PRBS error detector.
Table 56 - PRBS Error Counter
(Page 4, Address 10H) (T1)
Bit
Name
Functional Description
7 - 0 PSM7-0 This counter is incremented for each
received CRC multiframe. It is
cleared when the PRBS Error
Counter is written to.
Table 57 - CRC Multiframe Counter for PRBS
(Page 4, Address 11H) (T1)
Bit
Name
Functional Description
7
D4YALML
D4 Yellow Alarm Latch
. This bit is
set if a D4 yellow alarm is detected
within a 600 millisecond integration
period. It is cleared after a read.
6
D4Y48L
D4
milliseconds) Latch
. This bit is
set if a D4 yellow alarm is detected
within a 48 millisecond integration
period. It is cleared after a read.
Yellow
Alarm
(48
5
SECYELL
Secondary D4 Yellow Alarm
Latch
. This bit is set if an alternate
D4 (S bit in 12 th frame) is
detected. It is cleared after a read.
4
ESFYELL
ESF Yellow Alarm Latch
. This bit
is set upon receipt of a ESF yellow
alarm. It is cleared after a read.
3
BLUEL
Blue Alarm Latch
. This bit is set
upon receipt of a blue alarm. It is
cleared after a read.
2
PDVL
Pulse Density Violation Latch
.
This bit is set upon receipt of a
pulse density violation. It is cleared
after a read.
1
LLEDL
Line Loopback Enable Detect
Latch
. This bit is set upon receipt
of a line loopback enable code. It is
cleared after a read.
0
LLDDL
Line Loopback Disable Detect
Latch
. This bit is set upon receipt
of a line loopback disable code. It
is cleared after a read.
Table 58 - Alarm Reporting Latch
(Page 4, Address 12H) (T1)
Bit
Name
Functional Description
7 - 0 FC7 - 0
Framing Bit Counter
. This eight bit
counter will be incremented for each
error in the received framing pattern.
In ESF mode the ESF framing bits
are monitored. In D4 mode Fs bits
may be monitored as well as Ft bits.
See - Section 15.5 Framing Bit
Counter. The count is only active if
the MT9074 is in synchronization.
Table 59 - Framing Bit Counter
(Page 4, Address 13H) (T1)
相關(guān)PDF資料
PDF描述
MT9075B E1 Single Chip Transceiver
MT9075B E1 Single Chip Transceiver(E1單片收發(fā)器)
MT9075 E1 Single Chip Transceiver
MT9075A E1 Single Chip Transceiver
MT9075AL E1 Single Chip Transceiver
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT9074_05 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1/J1 Single Chip Transceiver
MT9074AL 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays 制造商:Zarlink Semiconductor Inc 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AL1 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 100MQFP - Trays
MT9074AP 制造商:Microsemi Corporation 功能描述:
MT9074AP1 制造商:Microsemi Corporation 功能描述:T1/E1/J1 SGLE CHIP XSCR 制造商:Microsemi Corporation 功能描述:FRAMER E1/J1/T1 5V 68PLCC - Rail/Tube 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC TXRX SGL T1/E1 68PLCC 制造商:Microsemi Corporation 功能描述:IC TXRX SGL T1/E1 68PLCC
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