參數(shù)資料
型號(hào)： MT90401AB
廠商： ZARLINK SEMICONDUCTOR INC
元件分類： 數(shù)字傳輸電路
英文描述： 150MA LOW-DROPOUT VOLTAGE REGULATOR SO-8 PKG
中文描述： ATM/SONET/SDH SUPPORT CIRCUIT, PQFP80
封裝： 14 X 14 MM, 1.40 MM HEIGHT, MS-026BEC, LQFP-80
文件頁(yè)數(shù)： 6/38頁(yè)
文件大小： 650K
代理商： MT90401AB
MT90401
Data Sheet
6
Zarlink Semiconductor Inc.
62
OE
Output Enable (Input)
. Tie high for normal operation. Tie low to force output clocks pins
F16, F8, C16, C8, C4, C2 to a high impedance state.
63
CS
Chip Select (5 V tolerant Input)
. This active low input enables the non-multiplexed
Motorola parallel microprocessor interface of the MT90401. When CS is set to high, the
microprocessor interface is idle and all bus I/O pins will be in a high impedance state.
64
RST
RESET (5 V tolerant Input).
This active low input puts the MT90401 in a reset condition.
RST should be set to high for normal operation. The MT90401 should be reset after power-
up and after the selected reference frequency is changed. The RST pin must be held low for
a minimum of 1msec. to reset the device properly.
65
HW
Hardware Mode (Input)
. If this pin is tied low, the device is in microport mode and is
controlled via the microport. If it is tied high, the device is in hardware mode and is
controlled via the control pins MS1, MS2, FS1, FS2, FLOCK and SONET/SDH.
66-69
D0 - D3
Data 0 to Data 3 (5 V tolerant Three-state I/O)
. These signals combined with D4-D7 form
the bidirectional data bus of the parallel processor interface (D0 is the least significant bit).
70
V
SS8
IC
Digital ground.
0 Volts.
71
Internal Connection.
Tie low for normal operation.
72
IC
Internal Connection.
Tie low for normal operation.
73
V
DD5
D4 - D7
Positive Power Supply.
Digital supply.
74-77
Data 4 to Data 7 (5 V tolerant Three-state I/O).
These signals combined with D0-D3 form
the bidirectional data bus of the parallel processor interface (D7 is the most significant bit).
78
R/W
Read/Write Select (5 V tolerant Input).
This input controls the direction of the data bus
D[0:7] during a microprocessor access. When R/W is high, the parallel processor is reading
data from the MT90401. When low, the parallel processor is writing data to the MT90401.
79
A0
Address 0 (5 V tolerant Input).
Address input for the parallel processor interface. A0 is the
least significant input.
80
IC
Internal Connection.
Tie low for normal operation.
Pin Description (continued)
Pin #
Name
Description
相關(guān)PDF資料
PDF描述
MT90401AB1 SONET/SDH System Synchronizer
MT9040 T1/E1 Synchronizer
MT9040AN T1/E1 Synchronizer
MT9043 T1/E1 System Synchronizer
MT9043AN T1/E1 System Synchronizer
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
MT90401AB1 制造商:Microsemi Corporation 功能描述:FRAMER SDH/SONET 3.3V 80LQFP EP - Trays 制造商:MICROSEMI CONSUMER MEDICAL PRODUCT GROUP 功能描述:IC SYNCHRONIZER SONET/SDH 80LQFP 制造商:Microsemi Corporation 功能描述:IC SYNCHRONIZER SONET/SDH 80LQFP
MT9040AN 制造商:ZARLINK 制造商全稱:Zarlink Semiconductor Inc 功能描述:T1/E1 Synchronizer
MT9040AN1 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Rail/Tube
MT9040ANR1 制造商:Microsemi Corporation 功能描述:FRAMER E1 /T1 3.3V 48SSOP - Tape and Reel
MT9041 制造商:MITEL 制造商全稱:Mitel Networks Corporation 功能描述:Multiple Output Trunk PLL
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