參數(shù)資料
型號(hào): MT58L256V18P1
廠商: Micron Technology, Inc.
英文描述: 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb,流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
中文描述: 256 × 18,流水線,SCD的SyncBurst的SRAM(4MB,在流水線式,單循環(huán)取消選擇,同步脈沖靜態(tài)存儲(chǔ)器)
文件頁數(shù): 24/28頁
文件大小: 445K
代理商: MT58L256V18P1
24
4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PRELIMINARY
READ/WRITE TIMING
6
(READ/WRITE timing parameters are contained on the following page.)
tKC
tKL
CLK
ADSP#
tADSH
tADSS
ADDRESS
tKH
OE#
ADSC#
CE#
(NOTE 2)
tAH
tAS
A2
tCEH
tCES
BWE#,
BWa#-BWd#
(NOTE 4)
Q
High-Z
ADV#
Single WRITE
D(A3)
A4
A5
A6
D(A5)
D(A6)
D
BURST READ
Back-to-Back READs
(NOTE 5)
High-Z
Q(A2)
Q(A1)
Q(A4)
Q(A4+1)
Q(A4+2)
tWH
tWS
Q(A4+3)
tOEHZ
tDH
tDS
tOELZ
(NOTE 1)
tKQLZ
tKQ
Back-to-Back
WRITEs
A1
DON’T CARE
UNDEFINED
A3
NOTE:
1. Q(A4) refers to output from address A4. Q(A4 + 1) refers to output from the next internal burst address following A4.
2. CE2# and CE2 have timing identical to CE#. On this diagram, when CE# is LOW, CE2# is LOW and CE2 is HIGH. When
CE# is HIGH, CE2# is HIGH and CE2 is LOW.
3. The data bus (Q) remains in High-Z following a WRITE cycle unless an ADSP#, ADSC# or ADV# cycle is performed.
4. GW# is HIGH.
5. Back-to-back READs may be controlled by either ADSP# or ADSC#.
6. Timing is shown assuming that the device was not enabled before entering into this sequence.
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