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4Mb: 256K x 18, 128K x 32/36 Pipelined, SCD SyncBurst SRAM
MT58L256L18P1_2.p65 – Rev. 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2000, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
PIPELINED, SCD SYNCBURST SRAM
PRELIMINARY
FEATURES
Fast clock and OE# access times
Single +3.3V +0.3V/-0.165V power supply (V
DD
)
Separate +3.3V or +2.5V isolated output buffer
supply (V
DD
Q)
SNOOZE MODE for reduced-power standby
Single-cycle deselect (Pentium
BSRAM-compat-
ible)
Common data inputs and data outputs
Individual BYTE WRITE control and GLOBAL
W RITE
Three chip enables for simple depth expansion
and address pipelining
Clock-controlled and registered addresses, data
I/Os and control signals
Internally self-timed WRITE cycle
Burst control pin (interleaved or linear burst)
Automatic power-down for portable applications
165-pin FBGA package
100-pin TQFP package
Low capacitive bus loading
x18, x32, and x36 versions available
OPTIONS
Timing (Access/Cycle/MHz)
2.3ns/4ns/250 MHz
2.6ns/4.4ns/225 MHz
3.1ns/5ns/200 MHz
3.5ns/6ns/166 MHz
4.0ns/7.5ns/133 MHz
5ns/10ns/100 MHz
Configurations
3.3V I/O
256K x 18
128K x 32
128K x 36
2.5V I/O
256K x 18
128K x 32
128K x 36
Packages
100-pin TQFP
165-pin FBGA
Operating Temperature Range
Commercial (0°C to +70°C)
Part Number Example:
*A Part Marking Guide for the FBGA devices can be found on Micron’shttp://www.micronsemi.com/support/index.html.
MARKING*
-4
-4.4
-5
-6
-7.5
-10
MT58L256L18P1
MT58L128L32P1
MT58L128L36P1
MT58L256V18P1
MT58L128V32P1
MT58L128V36P1
T
F
None
MT58L256L18P1, MT58L128L32P1,
MT58L128L36P1; MT58L256V18P1,
MT58L128V32P1, MT58L128V36P1
3.3V V
DD
, 3.3V or 2.5V I/O, Pipelined, Single-Cycle
Deselect
4Mb SYNCBURST
SRAM
**JEDEC-standard MS-026 BHA (LQFP).
100-Pin TQFP**
165-Pin FBGA
(Preliminary Package Data)
GENERAL DESCRIPTION
The Micron
SyncBurst
SRAM family employs
high-speed, low-power CMOS designs that are fabri-
cated using an advanced CMOS process.
Micron’s 4Mb SyncBurst SRAMs integrate a
256K x 18, 128K x 32, or 128K x 36 SRAM core with
advanced synchronous peripheral circuitry and a 2-bit
burst counter. All synchronous inputs pass through
registers controlled by a positive-edge-triggered single
clock input (CLK). The synchronous inputs include all
addresses, all data inputs, active LOW chip enable
(CE#), two additional chip enables for easy depth ex-
pansion (CE2, CE2#), burst control inputs (ADSC#,
ADSP#, ADV#), byte write enables (BWx#) and global
write (GW#).