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參數(shù)資料
| 型號： | MT58L128L36D1 |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 128K x 36，3.3V I/O Pipelined, DCD SyncBurst SRAM(4Mb，3.3V輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| 中文描述： | 128K的x 36,3.3六/輸出流水線，雙氰胺SyncBurst的SRAM（4MB，在3.3V的輸入/輸出，流水線式，雙循環(huán)取消選擇，同步脈沖靜態(tài)存儲器） |
| 文件頁數(shù)： | 16/24頁 |
| 文件大?。?/td> | 425K |
| 代理商： | MT58L128L36D1 |
16
4Mb: 256K x 18, 128K x 32/36 3.3V I/O Pipelined, DCD SyncBurst SRAM
MT58L256L18D1_2.p65 – Rev 8/00
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1999, Micron Technology, Inc.
4Mb: 256K x 18, 128K x 32/36
3.3V I/O PIPELINED, DCD SYNCBURST SRAM
PRELIMINARY
NOTE:
1. Test conditions as specified with the output loading shown in Figure 1 unless otherwise noted.
2. Measured as HIGH above V
IH
and LOW below V
IL
.
3. This parameter is measured with the output loading shown in Figure 2 unless otherwise noted.
4. This parameter is sampled.
5. Transition is measured ±500mV from steady state voltage.
6. Refer to Technical Note TN-58-09, “ Synchronous SRAM Bus Contention Design Considerations,” for a more thorough
discussion on these parameters.
7. OE# is a “ Don’t Care” when a byte write enable is sampled LOW.
8. A WRITE cycle is defined by at least one byte write enable LOW and ADSP# HIGH for the required setup and hold
times. A READ cycle is defined by all byte write enables HIGH and ADSC# or ADV# LOW or ADSP# LOW for the
required setup and hold times.
9. This is a synchronous device. All addresses must meet the specified setup and hold times for all rising edges of CLK
when either ADSP# or ADSC# is LOW and chip enabled. All other synchronous inputs must meet the setup and hold
times with stable logic levels for all rising edges of clock (CLK) when the chip is enabled. Chip enable must be valid at
each rising edge of CLK when either ADSP# or ADSC# is LOW to remain enabled.
ELECTRICAL CHARACTERISTICS AND RECOMMENDED AC OPERATING CONDITIONS
(Note 1) (0°C
￡
T
A
￡
+70°C; V
DD
, V
DD
Q = +3.3V +0.3V/-0.165V unless otherwise noted)
-6
-7.5
-10
DESCRIPTION
Clock
Clock cycle time
Clock frequency
Clock HIGH time
Clock LOW time
Output Times
Clock to output valid
Clock to output invalid
Clock to output in Low-Z
Clock to output in High-Z
OE# to output valid
OE# to output in Low-Z
OE# to output in High-Z
Setup Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
Hold Times
Address
Address status (ADSC#, ADSP#)
Address advance (ADV#)
Write signals
(BWa#-BWd#, BWE#, GW#)
Data-in
Chip enables (CE#, CE2#, CE2)
SYMBOL
MIN
MAX
MIN
MAX
MIN
MAX
UNITS
NOTES
t
KC
f
KF
t
KH
t
KL
6.0
7.5
10
ns
166
133
100
MHz
ns
ns
2.3
2.3
2.5
2.5
3.0
3.0
2
2
t
KQ
t
KQX
t
KQLZ
t
KQHZ
t
OEQ
t
OELZ
t
OEHZ
3.5
4.0
5.0
ns
ns
ns
ns
ns
ns
ns
1.5
0
1.5
0
1.5
1.5
3
3, 4, 5, 6
3, 4, 5, 6
7
3, 4, 5, 6
3, 4, 5, 6
3.5
3.5
4.2
4.2
5.0
5.0
0
0
0
3.5
4.2
4.5
t
AS
t
ADSS
t
AAS
t
WS
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
2.0
2.0
2.0
2.0
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
DS
t
CES
1.5
1.5
1.5
1.5
2.0
2.0
ns
ns
8, 9
8, 9
t
AH
t
ADSH
t
AAH
t
WH
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
ns
ns
8, 9
8, 9
8, 9
8, 9
t
DH
t
CEH
0.5
0.5
0.5
0.5
0.5
0.5
ns
ns
8, 9
8, 9
相關PDF資料 |
PDF描述 |
|---|---|
| MT58L128L32P1 | 128K x 32，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L128L36P1 | 128K x 36，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L128V32P1 | 128K x 32， Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L256L18P1 | 256K x 18,Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
| MT58L256V18P1 | 256K x 18，Pipelined, SCD SyncBurst SRAM(4Mb，流水線式，單循環(huán)取消選擇，同步脈沖靜態(tài)存儲器) |
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