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參數(shù)資料
| 型號： | MT4C4007J |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 1 Meg x 4 EDO DRAM(1M x 4擴(kuò)展數(shù)據(jù)輸出動(dòng)態(tài)RAM) |
| 中文描述： | 1梅格× 4 EDO公司的DRAM（3米× 4擴(kuò)展數(shù)據(jù)輸出動(dòng)態(tài)內(nèi)存） |
| 文件頁數(shù)： | 2/16頁 |
| 文件大?。?/td> | 204K |
| 代理商： | MT4C4007J |
1 Meg x 4 EDO DRAM
D23.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
2
1 MEG x 4
EDO DRAM
OBSOLETE
goes HIGH, as long as RAS# and OE# are held LOW and
WE# is held HIGH. Although OE# will function and con-
trol the outputs, OE# should be grounded as OE#-related
timing parameters are not tested. The use of this device
assumes OE# is grounded.
During cycles other than PAGE-MODE READ, the out-
puts are disabled at
t
OFF time after RAS# and CAS# are
HIGH, or
t
WHZ after WE# transitions LOW. The
t
OFF time
is referenced from the rising edge of RAS# or CAS#, which-
ever occurs last. WE# can also perform the function of
turning off the output drivers under certain conditions, as
shown in Figure 1.
EDO PAGE MODE (continued)
V
IL
CAS#
V
IL
RAS#
V
IL
ADDR
ROW
COLUMN (A)
DON’T CARE
UNDEFINED
V
IL
WE#
V
IOL
OPEN
DQ
tWPZ
The DQs go to High-Z if WE# falls and, if
t
WPZ is met,
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
V
IL
OE#
VALID DATA (B)
tWHZ
WE# may be used to disable the DQs to prepare
for input data in an EARLY WRITE cycle. The DQs
will remain High-Z until CAS# goes LOW with
WE# HIGH (i.e., until a READ cycle is initiated).
tWHZ
COLUMN (D)
VALID DATA (A)
COLUMN (B)
COLUMN (C)
INPUT DATA (C)
Figure 1
OUTPUT ENABLE AND DISABLE USING WE#
REFRESH
Preserve correct memory cell data by maintaining power
and executing any RAS# cycle (READ, WRITE) or RAS#
refresh cycle (RAS#-ONLY, CBR or HIDDEN) so that all
1,024 combinations of RAS# addresses (A 0-A9) are ex-
ecuted within
t
REF (MAX), regardless of sequence. The
CBR REFRESH cycle will invoke the internal refresh counter
for automatic RAS# addressing.
An optional Extended Refresh mode is also available on
the MT4C4007J L. The “L” version allows the user a dy-
namic refresh mode at the extended refresh period of 128ms.
STANDBY
Returning RAS# and CAS# HIGH terminates a memory
cycle and decreases chip current to a reduced standby level.
The chip is preconditioned for the next cycle during the
RAS# HIGH time.
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