- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄384756 > MT4C4007J (Micron Technology, Inc.) 1 Meg x 4 EDO DRAM(1M x 4擴展數(shù)據(jù)輸出動態(tài)RAM) PDF資料下載
參數(shù)資料
| 型號： | MT4C4007J |
| 廠商： | Micron Technology, Inc. |
| 英文描述： | 1 Meg x 4 EDO DRAM(1M x 4擴展數(shù)據(jù)輸出動態(tài)RAM) |
| 中文描述： | 1梅格× 4 EDO公司的DRAM（3米× 4擴展數(shù)據(jù)輸出動態(tài)內(nèi)存） |
| 文件頁數(shù)： | 1/16頁 |
| 文件大?。?/td> | 204K |
| 代理商： | MT4C4007J |
1 Meg x 4 EDO DRAM
D23.pm5 – Rev. 3/97
Micron Technology, Inc., reserves the right to change products or specifications without notice.
1997, Micron Technology, Inc.
1
1 MEG x 4
EDO DRAM
OBSOLETE
DRAM
FEATURES
Single +5V
±
10% power supply
JEDEC-standard pinout and packages
High-performance CMOS silicon-gate process
All inputs, outputs and clocks are TTL-compatible
Refresh modes: RAS#-ONLY, CAS#-BEFORE- RAS#
(CBR), HIDDEN; optional Extended
Extended Data-Out (EDO) PAGE MODE access cycle
1,024-cycle Extended Refresh distributed across 16ms
or 128ms
OPTIONS
Timing
60ns access
Refresh Rates
Standard Refresh (16ms period)
Extended Refresh (128ms period)
Package
Plastic SOJ (300 mil)
Part Number Example: MT4C4007JDJ-6 L
MARKING
-6
None
L
DJ
The four data inputs and four data outputs are routed
through four pins using common I/ O, and pin direction is
controlled by WE# and OE#.
PAGE ACCESS
PAGE operations allow faster data operations (READ or
WRITE) within a row address-defined (A0-A9) page
boundary.
The PAGE cycle is always initiated with a row address
strobed-in by RAS#, followed by a column address
strobed-in by CAS#. CAS# may be toggled-in by holding
RAS# LOW and strobing-in different column addresses,
thus executing faster memory cycles. Returning RAS# HIGH
terminates PAGE operation.
EDO PAGE MODE
The MT4C4007J provides EDO PAGE MODE, which is
an accelerated FAST PAGE MODE cycle. The primary
advantage of EDO is the availability of data-out even after
CAS# goes back HIGH. EDO provides for CAS# precharge
time (
t
CP) to occur without the output data going invalid.
This elimination of CAS# output control provides for pipe-
line READs.
FAST PAGE MODE DRAMs have traditionally turned
the output buffers off (High-Z) with the rising edge of
CAS#. EDO operates as any DRAM READ or FAST-PAGE-
MODE READ, except data will be held valid after CAS#
KEY TIMING PARAMETERS
Speed
-6
t
RC
110ns
t
RAC
60ns
t
PC
26ns
t
AA
30ns
t
CAC
17ns
t
CAS
13ns
MT4C4007J
GENERAL DESCRIPTION
The MT4C4007J is a randomly accessed, solid-state
memory containing 4,194,304 bits organized in a x4
configuration. During READ or WRITE cycles, each of the
4 memory bits (1 bit per DQ) is uniquely addressed through
the 20 address bits, which are entered 10 bits (A0-A9) at a
time. RAS# latches the first 10 bits and CAS# latches the
latter 10 bits.
A READ or WRITE cycle is selected with the WE# input.
A logic HIGH on WE# dictates READ mode, while a logic
LOW on WE# dictates WRITE mode. During a WRITE
cycle, data-in (D) is latched by the falling edge of WE# or
CAS#, whichever occurs last; however, only EARLY WRITE
cycles are supported (WE# falls prior to CAS#). LATE
WRITE cycles should not be attempted as the results are not
predictable. When WE# goes LOW prior to CAS# going
LOW (EARLY WRITE cycle), the output pins remain open
(High-Z) until the next CAS# cycle.
Note:
The “#” symbol indicates signal is active LOW.
PIN ASSIGNMENT (Top View)
20/26-Pin SOJ
(DA-1)
DQ1
DQ2
WE#
RAS#
A9
A0
A1
A2
A3
Vcc
Vss
DQ4
DQ3
CAS#
OE#
A8
A7
A6
A5
A4
1
2
3
4
5
9
10
11
12
13
26
25
24
23
22
18
17
16
15
14
相關PDF資料 |
PDF描述 |
|---|---|
| MT4C4M4A1 | DRAM |
| MT4C4M4Ax | DRAM |
| MT4LC4M4B1TG-6 | DRAM |
| MT4LC4M4A1TG-6 | DRAM |
| MT4C4M4B1TG-6 | DRAM |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| MT4C4256 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 4RAM(FAST PAGE MODE) |
| MT4C4256-10 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 4RAM(FAST PAGE MODE) |
| MT4C4256-12 | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:256K X 4RAM(FAST PAGE MODE) |
| MT4C425628 | 制造商:MICRON 功能描述:* |
| MT4C4256-6 | 制造商:MAJOR 功能描述: |
發(fā)布緊急采購，3分鐘左右您將得到回復。