參數(shù)資料
型號(hào)： MT48LC4M32LFFC
廠商： Micron Technology, Inc.
英文描述： SYNCHRONOUS DRAM
中文描述： 同步DRAM
文件頁數(shù)： 27/52頁
文件大?。?/td> 1281K
代理商： MT48LC4M32LFFC
27
128Mb: x32 SDRAM
128MbSDRAMx32_D.p65 – Rev. D; Pub. 6/02
Micron Technology, Inc., reserves the right to change products or specifications without notice.
2002, Micron Technology, Inc.
128Mb: x32
SDRAM
TRUTH TABLE 3 – CURRENT STATE BANK
n
, COMMAND TO BANK
n
(Notes: 1-6; notes appear below and on next page)
CURRENT STATE
Any
CS# RAS# CAS# WE#
H
X
L
H
L
L
L
L
L
L
L
L
L
H
L
H
L
L
L
H
L
H
L
L
L
H
L
H
L
H
L
L
L
H
COMMAND (ACTION)
COMMAND INHIBIT (NOP/Continue previous operation)
NO OPERATION (NOP/Continue previous operation)
ACTIVE (Select and activate row)
AUTO REFRESH
LOAD MODE REGISTER
PRECHARGE
READ (Select column and start READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Deactivate row in bank or banks)
READ (Select column and start new READ burst)
WRITE (Select column and start WRITE burst)
PRECHARGE (Truncate READ burst, start PRECHARGE)
BURST TERMINATE
READ (Select column and start READ burst)
WRITE (Select column and start new WRITE burst)
PRECHARGE (Truncate WRITE burst, start PRECHARGE)
BURST TERMINATE
NOTES
X
H
H
L
L
H
L
L
H
L
L
H
H
L
L
H
H
X
H
H
H
L
L
H
L
L
H
L
L
L
H
L
L
L
Idle
7
7
11
10
10
8
10
10
8
9
10
10
8
9
Row Active
Read
(Auto
Precharge
Disabled)
Write
(Auto
Precharge
Disabled)
NOTE:
1. This table applies when CKE
n-1
was HIGH and CKE
n
is HIGH (see Truth Table 2) and after
t
XSR has been
met (if the previous state was self refresh).
2. This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the
commands shown are those allowed to be issued to that bank when in that state. Exceptions are
covered in the notes below.
3. Current state definitions:
Idle:
The bank has been precharged, and
t
RP has been met.
Row Active:
A row in the bank has been activated, and
t
RCD has been met. No data bursts/
accesses and no register accesses are in progress.
Read:
A READ burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
Write:
A WRITE burst has been initiated, with auto precharge disabled, and has not yet
terminated or been terminated.
4. The following states must not be interrupted by a command issued to the same bank. COMMAND
INHIBIT or NOP commands, or allowable commands to the other bank should be issued on any clock
edge occurring during these states. Allowable commands to the other bank are determined by its
current state and Truth Table 3, and according to Truth Table 4.
Precharging:
Starts with registration of a PRECHARGE command and ends when
t
RP is met.
Once
t
RP is met, the bank will be in the idle state.
Row Activating:
Starts with registration of an ACTIVE command and ends when
t
RCD is met. Once
t
RCD is met, the bank will be in the row active state.
Read w/Auto
Precharge Enabled:
Starts with registration of a READ command with auto precharge enabled and
ends when
t
RP has been met. Once
t
RP is met, the bank will be in the idle state.
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